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Semiconductor device and its manufacture method

A manufacturing method and semiconductor technology, applied in semiconductor/solid-state device manufacturing, transistors, electrical components, etc., can solve the problems of device reliability degradation, degradation, and current gain reduction, and achieve the effect of increasing process costs.

Active Publication Date: 2010-05-12
UNITED MICROELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, for some P-type devices, it will degrade the reliability of the device (degradation)
For example, forming a compressive stress layer on the P-type metal oxide semiconductor transistor of the output and input (I / O), there will be a phenomenon of threshold voltage (threshold voltage, Vt) shift (shift), resulting in negative bias temperature Instability (negative bias temperature instability, NBTI) produces degradation, thereby reducing current gain and affecting device performance

Method used

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  • Semiconductor device and its manufacture method
  • Semiconductor device and its manufacture method
  • Semiconductor device and its manufacture method

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Embodiment Construction

[0037] Figure 1A to Figure 1D It is a schematic cross-sectional view of a manufacturing method of a semiconductor device according to an embodiment of the present invention.

[0038] First, please refer to Figure 1A , providing a substrate 100 . A first-type MOS transistor 102 , an I / O second-type MOS transistor 104 and a core second-type MOS transistor 106 have been formed on the substrate 100 . As mentioned above, the first type MOS transistor 102 , the input / output second type MOS transistor 104 and the core second type MOS transistor 106 are separated by the isolation structure 108 . Here, the isolation structure 108 is, for example, a shallow trench isolation structure.

[0039] As mentioned above, the I / O second-type MOS transistor 104 is an I / O MOS transistor, and the core second-type MOS transistor 106 is a core (core) MOS transistor. Wherein, the first-type MOS transistor 102 is, for example, an N-type MOS transistor, and the input-output second-type MOS transist...

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Abstract

The preparation method for semi-conductor device comprises: providing a substrate formed a first-type MOS transistor, an I / O second-type MOS transistor, and a core MOS transistor; forming a first stress layer to cover former elements; then, removing at least the stress layer on the second-type transistor to hold the stress layer on the first-type transistor; finally, forming the second stress layer on the second-type MOS transistor.

Description

technical field [0001] The present invention relates to an integrated circuit device and its manufacturing method, and in particular to a semiconductor device and its manufacturing method. Background technique [0002] In the development of integrated circuit devices, high-speed operation and low power consumption can be achieved by reducing the size of the devices. However, since the current technology for shrinking the device size is limited by factors such as process technology bottlenecks and high costs, it is necessary to develop other technologies different from device shrinkage to improve the driving current of the device. Therefore, it has been proposed to use stress control to overcome the limit of device miniaturization. [0003] An existing method for increasing device performance by means of stress control is to selectively form a layer of high tension (contact etching stop layer, CESL) on the substrate according to whether the device is N-type or P-type. tensi...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/8234H01L21/8238H01L27/088H01L27/092
Inventor 李坤宪黄正同洪文翰丁世汎郑礼贤郑子铭梁佳文
Owner UNITED MICROELECTRONICS CORP