Dynamic clock system and method designed for low power

Abstract

The invention discloses a system for generating a number of clock signals in computer system. The said system comprises a circuit for generating a core clock signal, a system bus clock signal and a periphery clock signal. One of the frequency of the said clock signals can be adjusted or changed, with no need of changing the oscillation frequency of the other clock signals. The invention also discloses a method for for generating a number of clock signals in computer system.

Description

Technical field [0001] The present invention relates to a clock generation method and system of a computer system, and more particularly to a system and method for generating multiple clocks with multiple oscillation frequencies in a computer system. Background technique [0002] Processors (such as microprocessors, central processing units, etc.) are widely used in various products and applications, from desktop computers to portable electronic devices, such as mobile phones, laptop computers, and personal digital assistants (PDAs). Compared with low-end product processors with simplified designs and inexpensive products and applications, some processors emphasize their powerful performance (for example, processors used in high-end computer workstations). [0003] Usually efficiency and energy consumption are opposed to each other. Generally speaking, high-performance processors operate faster or have more complicated designs, and therefore consume more power than low-performanc...

AI Technical Summary

Problems solved by technology

However, as shown in the previous example, if the circuit design of the computer system is configured in series to generate synchronous clocks, since the system bus and peripheral clock signals are derived from the core clock signal, reducing the frequency of the core clock signal will also reduce the system bus with the frequency of the peripheral clock signal

As mentioned above, when the CPU is waiting for peripheral or bus operations to complete, reducing the frequency of the core clock signal according to this scheme will also reduce the frequency of the peripheral and system bus clock signals, while the system bus and / or peripheral bus Already busy, reducing the frequency of its clock signal will result in reduced system performance

[0008] Another disadvantage of reducing power consumption by reducing the frequency of the core clock signal when the system's CPU is idle, as shown in the example in Figure 1, is that the programmable clock divider used to derive the clock signal usually requires a One or more instructions to complete the configuration, in order to reduce the frequency of the core clock signal, such a system must execute one or more instructions to reprogram the frequency divider to reduce the frequency of the clock signal, and then must execute one or more instructions to make the clock The frequency of the signal is restored to standard or raised again, which is not an ideal proposal

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