CMOS device manufacturing method having different lateral wall bulkhead width

A device manufacturing method and sidewall spacing technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve threshold voltage, drive current and saturation leakage current differences, CMOS device performance symmetry and consistency degradation, etc. problem, the effect of reaching threshold voltage and saturation leakage current improvement

Inactive Publication Date: 2008-03-12
SEMICON MFG INT (SHANGHAI) CORP
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  • Abstract
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Problems solved by technology

This will lead to differences in the threshold voltage, drive current and saturation leakage current of NMOS and PMOS, which will degrade the performance of CMOS devices such as symmetry and consistency

Method used

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  • CMOS device manufacturing method having different lateral wall bulkhead width
  • CMOS device manufacturing method having different lateral wall bulkhead width
  • CMOS device manufacturing method having different lateral wall bulkhead width

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Embodiment Construction

[0014] In order to make the above objects, features and advantages of the present invention more comprehensible, specific implementations of the present invention will be described in detail below in conjunction with the accompanying drawings.

[0015] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, the present invention can be implemented in many ways other than those described here, and those skilled in the art can make similar extensions without departing from the connotation of the present invention. Accordingly, the invention is not limited to the specific implementations disclosed below.

[0016] In CMOS devices, the n-channel of NMOS and the p-channel of PMOS are formed on the same substrate, and the length of the channel is determined by the width of the sidewall spacer. The respective conduction characteristics of NMOS and PMOS transistors are obtained by performing ...

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Abstract

The invention discloses a manufacturing method for CMOS device with different distant width of the sidewall, which comprises: providing a semiconductor underlay, forming the first grid structure and the second grid structure on the said underlay; depositing the material layer of the sidewall distant side on the underlay with the first and second grid structures; etching to cover the material layer of the sidewall distant side of the first grid structure and protect to cover the material layer of the sidewall distant side of the second grid structure by mask; etching the said material layer to form sidewall distant side on both sides of the first grid structure and the second grid structure; making process of ion implanted impurity to form source electrode region and drain electrode region. With the method provided in the invention, the length of the sidewall distance side formed on both sides of the grids of the PMOS transistor is longer than that of the NMOS transistor, which improves the property of deep sub-micron CMOS device.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for manufacturing CMOS (Complementary Metal Oxide Semiconductor) devices with different widths of sidewall spacers. Background technique [0002] With the rapid development of semiconductor manufacturing technology, in order to achieve faster computing speed, larger data storage capacity and more functions of semiconductor devices, semiconductor wafers are developing towards higher component density and high integration. The gate of CMOS devices The pole feature size has entered the deep submicron stage, and the gate length has become thinner and shorter than before. Currently, a lightly doped drain (LDD) structure (commonly referred to as extended doping) and shallow source / drain junction regions are used to avoid short channel effects. However, due to the shallowing of the lightly doped region and the junction region, the resistance of the source a...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/8238
Inventor 何德飚蔡孟峰
Owner SEMICON MFG INT (SHANGHAI) CORP
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