Register circuit, scanning register circuit applying same and scanning method

Abstract

The present invention provides a register circuit, which includes a latch circuit for latching an input data and generating an output data; an input signal selecting circuit, which is coupled with a non-testing data and a testing date respectively, and is used to selectively output the non-testing data and the testing date to act as the input date; a control circuit, which is coupled on a drive clock, and is used to determine the output date according to that the drive clock controls whether the latch circuit can latch the input data; and a scan circuit, which is coupled on the drive clock and the latch circuit, and is used to generate a scan date according to the output date outputted by the drive clock scanning the latch circuit.

Description

technical field [0001] The invention relates to a circuit testing device and method, in particular to a register circuit applied to domino CMOS logic, a scan register circuit using the register circuit and a scanning method thereof. Background technique [0002] In order to improve the operation speed of the circuit, it has become the trend of today's digital logic circuits for designers to replace static circuits with dynamic circuits. Among them, dynamic circuits include domino CMOS conductor logic circuits, differential Dynamic cascade voltage swing logic circuit (Differential cascade voltage swing logic) and so on. Taking the domino CMOS logic circuit as an example, it uses a virtual N-type field-effect transistor (pseudo NMOS) architecture to implement its logic circuit. Compared with static circuits, this will greatly reduce the required power. The number of transistors, and the domino CMOS logic circuit has a small charge delay (pull-up delay) and a negligible short-...

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Problems solved by technology

[0003] However, in fact, the biggest problem faced by the CMOS logic circuit of the domino is the test part after the chip is completed, and the test methods disclosed in the prior art all assume the CMOS logic circuit of the domino It is composed of purelycombinational domino gates. This test method is not suitable for sequential domino logic gates. Therefore, most designers today still combine dynamic circuits with static circuits. to design

[0004] According to the teaching of "DOMINO SCAN ARCHITECTURE ANDDOMINO SCAN FLIP-FLOP FOR THE TESTING OF DOMINO AND HYBRID CMOS CIRCUITS" disclosed in U.S. Patent No. 6,108,805, it can be known that it has three disadvantages: first, due to the domino scanning of the prior art The unit is made up of multiple output stages, so the time for an input data to generate an output data becomes longer; the second, because the prior art utilizes two control clocks in the process of operation, that is, the system clock and the domino clock, so to obtain correct results, it is necessary to precisely control the timing relationship between the system clock and the domino clock; the third, due to the duty cycle (Duty cycle) of the system clock and the domino clock that this prior art needs to utilize ) are inconsistent, thus increasing the difficulty of implementation

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