Semiconductor device and its production method

Abstract

The invention discloses a semiconductor device, which comprises an isolation layer dividing a silicon substrate into an active area and an inactive area, a gate formed on the silicon substrate, a gate formed around a side wall (side wall) of the gate a gate oxide layer for exposing the upper part of the sidewall of the gate, a gate insulating layer formed between the silicon substrate and the gate, an epitaxial layer formed above the gate and an active region surrounding the gate; A lightly doped drain region formed in the surface of the silicon substrate surrounding the gate; a gate spacer formed around the sidewall of the gate including the gate oxide layer; formed on two sides of the gate spacer A source region and a drain region in the surface of the silicon substrate on the side, and a protective layer formed over the entire surface of the silicon substrate.

Description

[0001] This application claims priority from Korean Patent Application No. 10-2006-0088417 filed September 13, 2006, which is hereby incorporated by reference as if set forth in its entirety. technical field [0002] The present invention relates to a semiconductor device, and more particularly, to a semiconductor device and a method of manufacturing the same, which can easily control the short channel effect. Background technique [0003] A Field Effect Transistor (FET) is a transistor with a large number of charge carriers migrating from the source through the gate to the drain. One type of FET is the Metal Oxide Semiconductor Field Effect Transistor (MOSFET). MOSFETs exhibit good electrical characteristics and may be constructed to include an oxide layer formed on and / or over a silicon substrate and a silicon electrode formed on and / or over the oxide layer. This configuration allows the electric field to regulate the charge flow into the silicon surface. [0004] With t...

AI Technical Summary

Problems solved by technology

As shown in the example of Figure 3, the effective length of the gate channel decreases, which leads to an increase in the short channel effect

In addition, the increased overlap area of ​​the LDD region and the gate-channel leads to severe hot carrier effects and higher overlap capacitance between the gate and the source and drain regions

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