Double-port access symmetrical dynamic memory interface

Abstract

The invention relates to a computer interface, in particular to an interface of symmetrical dynamic memory with dual ports access. The invention eliminates the defects in the aspects of cost, memory capacity, system performance, usability, etc. existing in adopting dual port RAM device as a share memory and adopting time-sharing multiplexing technology of a bus to access to the share memory. The invention comprises a central control module, two processor interface modules, two memory interface modules, a refreshing module and an initialization module. The interface of the invention connects two dynamic memories with the same model and mirrored with each other as a share memory of the two processors, which realize that the two processors simultaneously access to the share memory without conflict through the interface under the requirements of high system performance and high speed processors.

Description

Interface for Dual-Port Access to Symmetric Dynamic Memory technical field The invention relates to a computer interface, in particular to an interface between a processor and a memory, in particular to an interface for double processor ports to access a symmetrical dynamic memory. Background technique In recent years, shared memory in multiprocessor systems is a research hotspot. Currently, there is only one access port to the shared memory, which increases the possibility of conflicts between multiprocessors accessing the shared memory. When there are two or more processors accessing the memory, only one processor is allowed to access the memory, and other processors are in a waiting state, that is, each processor cannot access the memory in parallel. In order to solve this problem, the technologies that are generally popular now mainly include: using dual-port RAM devices and time-division multiplexing technology using a bus. However, the current shared memory general...

AI Technical Summary

Problems solved by technology

In order to solve the problem that under the requirements of high system performance and high-speed processors, a shared memory cannot well meet the read and write timing requirements of the processor, the processor needs to increase the waiting period, thereby reducing the overall system performance. Provides a dual-port interface to symmetric dynamic memory

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