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Mechanism to generate logically dedicated read and write channels in a memory controller

A technology of memory controller and memory, applied in the field of computer systems

Inactive Publication Date: 2013-08-21
INTEL CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

A problem exists in a command scenario where each write command introduces at least two idle frames in the NB lane

Method used

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  • Mechanism to generate logically dedicated read and write channels in a memory controller
  • Mechanism to generate logically dedicated read and write channels in a memory controller
  • Mechanism to generate logically dedicated read and write channels in a memory controller

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Embodiment Construction

[0028] A mechanism for generating logically dedicated read and write channels in a memory controller that accesses FB-DIMM memory devices is described. In the following detailed description of the present invention, a large number of specific details are set forth in order to provide a sufficient understanding of the present invention. However, the present invention can be implemented without these specific details, which is obvious to those skilled in the art. In other examples, well-known structures and devices are shown in block diagrams instead of detailed descriptions, so as not to affect the understanding of the present invention.

[0029] The “one embodiment” or “an embodiment” mentioned in the specification means that the specific feature, structure, or characteristic described in conjunction with the embodiment is included in at least one embodiment of the present invention. The appearances of the phrase "in one embodiment" in different places in this specification do n...

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Abstract

According to one embodiment, a system is disclosed. The system includes a memory controller to schedule read commands to frames via a first dedicated command slot and to schedule write commands and corresponding data to frames via a dedicated second or third command slot.

Description

Technical field [0001] The present invention relates to a computer system; more specifically, the present invention relates to a memory controller (memory controller). Background technique [0002] Fully buffered DIMM (or FB-DIMM) dynamic random access memory (DRAM) memory devices provide memory solutions that can be used to increase the reliability, speed, and density of memory systems. Traditionally, the data line of the memory controller is connected to the data line of each DRAM module. As memory bandwidth and access speed increase, signals degrade at the interface between the interconnection and the device. This limits the speed and / or memory density. FB-DIMM devices use different methods to solve this problem. [0003] The FB-DIMM architecture includes an advanced memory buffer (AMB) between the memory controller and the memory module. Different from the parallel interconnection architecture of traditional DRAM, FB-DIMM has a serial interface between the memory controller...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C7/22G06F3/06
CPCG06F13/1668G11C7/10G11C11/409G06F12/00G06F9/06
Inventor R·苏巴什钱德拉博斯A·莫汉蒂R·阿加瓦尔
Owner INTEL CORP