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Double runs data coding method

A data encoding and run-length technology, applied in code conversion, electronic circuit testing, electrical components, etc., can solve problems such as negative growth of encoding rate

Inactive Publication Date: 2008-06-18
BEIJING UNIV OF POSTS & TELECOMM
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Problems solved by technology

[0009] It can be seen from Table 1 that the shortcomings and limitations of the Golomb data encoding method are only suitable for the case where the number of 0 or 1 in the test vector has an absolute advantage, such as the case where 0 accounts for 80% or 1 accounts for 80%.
In the Golomb data encoding method, only when there are more 0s or 1s in the original data than the other, a better encoding rate will appear, and when the two are almost the same, there will be a phenomenon of negative growth in the encoding rate

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Embodiment Construction

[0040] A double-run data encoding method according to the present invention will be further described in detail below in conjunction with the accompanying drawings and specific implementation methods. The double-run-length data encoding method (Double-Run-length) of the present invention is to divide the code length of data encoding into three parts: label bit, group bit and parity bit. As shown in Figure 1:

[0041] Marking bit: There is one bit, which is 1 or 0, indicating that the encoding is based on the run length of 1 or the run length of 0, 1 indicates that the code word is encoded according to the run length of 1, and 0 indicates that it is encoded based on the run length of 0;

[0042] Group bit: The group bit is an odd number, the start bit is 1, and the end bit is 0. Counting from the first 1, every two bits describe the nature of the group. The general format is 1x1x1x0..., where x is 0 or 1 until 0 is encountered, indicating the end of the group;

[0043] Parity...

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Abstract

The invention discloses a double-run data encoding method. The invention is characterized in that the code length of the data encoder consists of three parts: a mark bit, a domain bit and a parity bit. The invention has the advantages that the appearance times of 1 or 0 in original binary data are not taken into account, and 1 and 0 can be processed at the same time for the coding of a testing vector; ideal compressibility and higher coding rate can be obtained in all situations; the increment of the compressibility is faster than that of other data coding methods, and the negative compression phenomenon of the testing data can also be avoided. Therefore, the invention is extremely suitable for the compression of the testing vector of a system chip and provided with strong practical value.

Description

Technical field: [0001] The invention relates to a double-run data encoding method in the field of microelectronics. Background technique: [0002] Current IP manufacturers will provide corresponding test vectors when providing IP cores. These test vectors are not only used in design simulation on workstations, but also used in wafer silicon testing. For a complex system chip, its test vector is very large. For example, in the case of a system chip integrated with ARM7TDMI, the test vectors provided by ARM have nearly 1.1 million cycles of test vectors. Even if parallel testing is used, it can only reduce a certain number of test cycles, and there are 150,000 clock cycles. But at the same time, more test channels are required. For a silicon wafer test process, its cost is directly proportional to the required test time and the number of test channels. The best way to solve the problem of expensive test equipment is to use built-in self-test. However, not all modules can ...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M7/46G01R31/28
Inventor 邓中亮韩可
Owner BEIJING UNIV OF POSTS & TELECOMM
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