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Scan testing methods

A technology for testing vectors and testing integrated circuits, which is applied in the direction of measuring electricity, measuring devices, measuring electrical variables, etc.

Inactive Publication Date: 2011-04-13
NXP BV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0014] There is a limit to how fast the scan test cycle can run, and this limit is the maximum frequency of the scan clock signal 42

Method used

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Embodiment Construction

[0046] The present invention relates to a method of testing integrated circuits in which clock signals of different speeds are used to shift test vectors and results into and out of shift registers to obtain test results from the circuit under test. This enables improved design speed constraints while taking into account the propagation delay of the circuit under test.

[0047] The present invention is based on the identification of a number of factors that affect the maximum speed at which a vector-based test circuit, such as the circuit shown in FIG. 1, operates. These factors are discussed before describing the present invention.

[0048]There are four main limitations on how fast a circuit can operate.

[0049] (i) The time delay required between when the test vectors can enter the logic circuit and when the resulting data can be passed through the shift register (path from Q through logic unit 10 to DB in Figure 1). Insufficient delay can cause wrong data to be captured...

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Abstract

A method of testing an integrated circuit, comprises providing a test vector to a shift register arrangement by providing test vector bits in series into the shift register arrangement (20) timed with a first, scan, clock signal (42). The test vector bits are passed between adjacent portions of the shift register arrangement timed with the first clock signal (42) and an output response of the integrated circuit to the test vector is provided and analyzed. The output response of the integrated circuit to the test vector is provided under the control of a second clock signal (56) which is slower than the first clock signal. This testing method speeds up the process by increasing the speed of shifting test vectors and results into and out of the shift register, but without comprising the stability of the testing process. Furthermore, the method can be implemented without requiring additional complexity of the testing circuitry to be integrated onto the circuit substrate.

Description

technical field [0001] The present invention relates generally to the testing of semiconductor integrated circuits during manufacture, and more particularly to the testing of combinational logic arrays using scan test techniques. Background technique [0002] The scan test technique basically involves loading a test pattern (called a "vector") into the package pins of the device and monitoring the output response at a specific time depending on the clock speed of the device. A set of test vectors is used to determine the performance of the device under test. These vectors are designed so that manufacturing defects of the device can be detected. [0003] Increased integration density has greatly improved the functionality, performance, and economics of integrated circuit device fabrication due to the increased number of closely placed active elements that can be formed simultaneously on a wafer. However, the absence of manufacturing defects must be determined by passing a s...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G01R31/3185
CPCG01R31/318594
Inventor 劳伦特·苏伊夫迪代·盖罗
Owner NXP BV