Memory device employing three-level cells and related methods of managing

A storage device, three-level technology, applied in information storage, static memory, read-only memory, etc., can solve problems such as limitations

Active Publication Date: 2008-10-01
MICRON TECH INC
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

In practice, a program operation (1→0) may mean erasing (0→1) at least one correction cell: as mentioned earlier, this cannot be done to a single cell of a NOR FLASH storage device, but only to the entire cell to which the cell belongs. addressing sectors for
Therefore, the use of ECC in NOR FLASH memory devices severely limits the so-called "bit manipulation", the possibility of programming a single bit of the memory

Method used

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  • Memory device employing three-level cells and related methods of managing
  • Memory device employing three-level cells and related methods of managing
  • Memory device employing three-level cells and related methods of managing

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Embodiment Construction

[0042] In the multi-level memory device of the present invention, each cell can take one of three possible logical values, which has the advantage of making the area occupied less than that of a one-bit memory device per cell, and having a lower area than that of a two-bit memory device per cell. Distribution of a smaller number of storage devices. Therefore, error correcting codes are not necessarily used to ensure reliability, and this allows "bit manipulation" to be entirely feasible.

[0043] In order to store a string of bits in a tri-level memory cell in an efficient manner, the encoding operations for a binary string that can be stored in a ternary string in a tri-level memory cell, and vice versa, need to be properly defined. Such as Figure 5As shown, 'A', 'B' and 'C' are the three levels that each cell can adopt ('A' is the erasing level, 'B' and 'C' are the two programming levels), for For each pair of cells (3×3=9 possible states), associate 3 bits (2 3 = 8 poss...

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Abstract

The invention claims a memory device and related management method. The method adopts a three-level cell, wherein each pair of units stores three-bit strings in advance. Said memory device further includes a coding circuit and a decoding circuit for converting the three-bit string under storage in the write operation into two ternary strings to be written in the corresponding three-level cell, and for the contrary in the read operation. Each cell possibly has three states at most. As a result, the relative distribution of three different thresholds may be comparatively far away from the voltage level having worsened read interference phenomenon and contention phenomenon.

Description

technical field [0001] The present invention generally relates to semiconductor memory devices, and more particularly, to memories employing three-level cells and related management methods. Background technique [0002] A standard FLASH memory device basically comprises an array of one-bit memory cells, where each memory cell can assume two possible states corresponding to the two logic states ('1' or '0') of the bit. The two logic states are associated with different charges stored in the floating gate of the cell, ie with different threshold voltages of the cell. [0003] Typically, programmed cells (logic value '0') have a higher threshold voltage than erased cells (logic value '1'). Due to the statistical spread (spread) caused by various reasons, the actual threshold voltages of the erased cells and the programmed cells of the storage sector have generally as figure 1 The statistical distribution shown. [0004] Multilevel memory devices are based on cells that can ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C16/06G11C16/26G11C16/34G11C29/42
Inventor A·马格纳瓦卡M·斯科蒂N·德尔加托C·纳瓦M·弗拉里奥M·莫利切利
Owner MICRON TECH INC
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