Assembly line a/d converter and method for eliminating sampling-hold circuit

A sample-and-hold circuit, analog-to-digital converter technology, applied in analog-to-digital conversion, code conversion, instruments, etc., can solve problems such as low sampling rate, and achieve the effect of improving tolerance

Inactive Publication Date: 2008-10-08
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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Therefore, the traditional pipeline ADC sample-and-hold circuit eliminatio

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  • Assembly line a/d converter and method for eliminating sampling-hold circuit
  • Assembly line a/d converter and method for eliminating sampling-hold circuit
  • Assembly line a/d converter and method for eliminating sampling-hold circuit

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[0031] In order to make the objectives, technical solutions, and advantages of the present invention clearer, the following further describes the present invention in detail with reference to specific embodiments and drawings.

[0032] The invention provides a pipelined analog-to-digital converter that eliminates sample-and-hold circuits. The first-stage MDAC in the pipelined analog-to-digital converter adopts a 1.5-bit structure, so that the error correction range of the first-stage comparator is relatively large.

[0033]Further, the sampling-related switches in the first-stage MDAC circuit include Sc1, Sc2, Ss1, Ss2, Sf1, Sf2, and the sampling-related switches in the first-stage SUBADC include Sc3, Sc4, Sc5, Sc6, Ss3, Ss4, Ss5, Ss6, the pipeline analog-to-digital converter further uses the same clock signal ph1e to control Sc1, Sc2, Sc3, Sc4, Sc5 and Sc6, and uses the same clock signal ph1 to control Ss1, Ss2, Sf1, Sf2 Ss3, Ss4, Ss5, and Ss6 to eliminate the difference between ...

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Abstract

The invention relates to pipelining ADC technical field, discloses a pipelining ADC for eliminating the sample holding circuit, a first MDAC in the pipelining ADC adopts 1.5 bit structure. Meanwhile the invention also discloses a 10 bit pipelining ADC using the elimination sample holding circuit and a method for eliminating the sample holding circuit in the pipelining ADC. The invention improves tolerance degree of the voltage error and reduces error between the first stage MDA sample voltage and the first stage sub ADC sample voltage casued by different sample moment or sample time constants.

Description

technical field [0001] The invention relates to the technical field of pipeline analog-to-digital converters (Analog to Digital Circuit, ADC), in particular to a pipeline ADC that eliminates a sample-and-hold circuit and a method for eliminating a sample-and-hold circuit in a pipeline ADC, in particular to a 10-bit Pipeline ADC for sample and hold circuits. Background technique [0002] Pipeline ADC is currently the most obvious trade-off advantage in speed, accuracy, power consumption and area among ADCs. In a pipeline ADC, the performance requirements for the front-end sample-and-hold circuit are the highest, and its accuracy must reach the accuracy required by the entire ADC, so the power consumption is usually relatively large. In many pipeline ADCs, the power consumption of the sample-and-hold circuit accounts for to more than a third of the entire ADC. At the same time, the sample and hold circuit occupies a large chip area, and its noise contributes a lot to the ADC...

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Application Information

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IPC IPC(8): H03M1/38
Inventor 郑晓燕周玉梅
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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