Semiconductor device and method for fabricating the same

A semiconductor and device technology, applied in the field of semiconductor devices, can solve problems such as deterioration of refresh characteristics, reduction of data storage performance of DRAM cells, increase of leakage current in drain regions, etc.

Inactive Publication Date: 2008-10-15
SK HYNIX INC
View PDF1 Cites 5 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Taking the DRAM cell as an example, when the fin-pass transistor is turned off with a binary "1" voltage in the drain region, the phenomenon of gate-induced drain leakage ("GIDL") results in a Leakage current increases
Then, the data retention performance ("1" in this case) of the DRAM cell is lowered, which degrades the refresh characteristic of the DRAM

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Semiconductor device and method for fabricating the same
  • Semiconductor device and method for fabricating the same
  • Semiconductor device and method for fabricating the same

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0013] figure 1 is a layout showing a semiconductor device according to an embodiment of the present invention. The semiconductor device includes an active region 101 defined by a device isolation region 120 , a recessed gate region 103 , and a gate region 105 . The longitudinal direction of the gate region 105 is defined as "vertical direction", and the longitudinal direction of the active region 101 is defined as "horizontal direction". The recessed gate region 103 and the gate region 105 overlap. The figure shows that the horizontal line width of one side of the recessed gate region 103 is smaller than F by D (wherein, 0≦D<F / 2, and F is the distance between two adjacent gate regions 105 ). In other words, the horizontal line width of the recessed gate region 103 is F-2D.

[0014] figure 2 is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention. figure 2 (i) is along figure 1 The cross-sectional view taken by I-I′,...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

A semiconductor device comprises a fin-type active region defined by a semiconductor substrate having a device isolation structure, a recess formed over the fin-type active region, and a gate electrode including a silicon germanium (Si1-xGex) layer for fill the recess (where 0<X<1 and X is a Ge mole fraction).

Description

technical field [0001] The present invention generally relates to a semiconductor device. More particularly, the present invention relates to a semiconductor device including a fin transistor and a method of manufacturing the same. Background technique [0002] In Fin Channel Array Transistor (FCAT), the fin channel transistor has a three-dimensional structure in which a channel is surrounded by a tri-gate. Existing fabrication techniques can be used to fabricate the fin-like channel structure. The fin-shaped channel structure has a larger surface area to reduce the short channel effect between the drain region and the source region. The fin-shaped channel structure allows lower channel doping concentration, which reduces leakage current through the junction region. [0003] The lower gate electrode of the fin channel transistor includes a p+ polysilicon layer. The work function of the p+ polysilicon layer is greater than that of the p- silicon substrate. Taking the DRA...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/772H01L29/78H01L29/43H01L29/49H01L21/335H01L21/336H01L21/28
CPCH01L29/7851H01L29/66621H01L29/66795H01L29/7854H01L29/7833
Inventor 李相敦
Owner SK HYNIX INC
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products