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Manufacturing method of conductive blind hole on circuit substrate

A circuit substrate and conductive blind via technology, applied in the direction of electrical connection formation of printed components, etc., can solve the problems of peeling, electrical connection of conductive blind via patterned circuit layers, reducing the structural reliability of circuit substrates, etc., to increase bonding strength, The effect of improving reliability

Active Publication Date: 2008-10-15
ADVANCED SEMICON ENG INC
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, the thermal expansion of the circuit substrate in use will cause the part of the electroless copper plating layer in contact with the capture pad to be easily damaged by thermal stress and peel off.
The above peeling phenomenon will cause poor contact between the conductive blind via and the patterned circuit layer, which will easily cause the conductive blind via to fail to be electrically connected to the patterned circuit layer, thereby reducing the structural reliability of the circuit substrate.

Method used

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  • Manufacturing method of conductive blind hole on circuit substrate
  • Manufacturing method of conductive blind hole on circuit substrate
  • Manufacturing method of conductive blind hole on circuit substrate

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Embodiment Construction

[0023] In order to make the above objects and other objects, features and advantages of the present invention more comprehensible, preferred embodiments will be described in detail below together with the accompanying drawings.

[0024] Figure 2A to Figure 2E It is a sectional view of the manufacturing process of a conductive blind hole of a circuit substrate according to a preferred embodiment of the present invention. The manufacturing method of the conductive blind hole of this circuit substrate is as follows: first, as Figure 2A As shown, a circuit substrate 200 is provided, and the circuit substrate 200 includes a first dielectric layer 210, a patterned circuit layer 220 and a second dielectric layer 230, wherein the patterned circuit layer 220 is sandwiched between the first dielectric layer 210 and the second dielectric layer 230, and the above-mentioned first dielectric layer 210 can be a core layer. In addition, the patterned circuit layer 220 of this embodiment i...

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Abstract

The invention discloses a production method of a conducting blind hole of a wiring base plate, which comprises the steps: firstly, the wiring base plate which comprises a first dielectric layer, a patterning line layer and a second dielectric layer is provided. The patterning line layer is clamped and positioned between the first dielectric layer and the second dielectric layer and comprises at least one capturing pad; secondly, a blind hole is formed in the second dielectric layer, wherein, the blind hole exposes the capturing pad; thirdly, an electroless copper processing is processed so as to form an electroless copper layer on the inner wall of the blind hole and the capturing pad; fourthly, the electroless copper layer on the capturing pad is removed; finally, the blind hole is filled with conducting material to form the conducting blind hole.

Description

technical field [0001] The present invention relates to a manufacturing method of a circuit substrate, and in particular to a manufacturing method of a conductive blind via of a circuit substrate. Background technique [0002] The circuit substrate is mainly composed of a plurality of patterned circuit layers and a plurality of dielectric layers stacked alternately. Among them, the patterned circuit layer is defined by copper foil layer through lithographic etching; and the dielectric layer is arranged between the patterned circuit layers to protect and isolate each patterned circuit layer; and each patterned circuit layer is passed through The conductive vias in the dielectric layer are electrically connected to each other. In addition, a plurality of contacts are formed on the surface of the circuit substrate for electrical connection with external electronic components. In the current semiconductor packaging technology, because the circuit substrate has the advantages o...

Claims

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Application Information

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IPC IPC(8): H05K3/42
Inventor 王德峻
Owner ADVANCED SEMICON ENG INC