Wafer stage encapsulation method of chip dimension
A wafer-level chip and size packaging technology, which is applied in the manufacture of electrical components, electrical solid devices, semiconductor/solid devices, etc., can solve the problems of poor reliability of packaged components, poor control of the volume of the second solder bump, and increased detection Requirements and reassembly issues, to achieve the effect of increased density, easy detection and reassembly, and convenient volume
Inactive Publication Date: 2008-10-22
SEMICON MFG INT (SHANGHAI) CORP +1
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Problems solved by technology
[0011] In the wafer-level chip package described in the above patents, since the second solder bumps are directly fabricated on the first solder bumps, the volume of the second solder bumps cannot be well controlled, resulting in poor reliability of the packaged components. Increased need for follow-up testing and difficulty in reassembly
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[0028] The present invention aligns and reflows the first solder bump on the chip with the second solder layer on the substrate to form a second solder bump fixed to the first solder bump; the substrate is removed, leaving the first solder bump attached fixed second solder bump. Since the second solder bump is not directly formed on the first solder bump, but is formed after forming the second solder layer on the substrate aligned with the first solder bump and reflowed, the volume of the second solder bump is easy to control, It is easy for subsequent inspection and reassembly to ensure the performance and reliability of the device. In addition, in the present invention, since the melting temperature of the second solder layer is lower than the melting temperature of the first solder bump, the physical state of the first solder bump will not change during and after reflow. The solder bumps also increase the density of solder bumps on an integrated circuit with the same area....
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Abstract
A method for completing wafer level chip size package comprises the following steps that: a wafer having at least one chip is provided; the chip is provided with a bonding pad which comprises a first solder lug; a substrate layer is formed on a plaque; a second solder layer corresponding to the first solder lug is formed on the substrate layer; the first solder lug is aligned with the second solder layer, and the second solder layer is reflowed to form a second solder lug fixed with the first solder lug; the plaque is removed and the second solder lug is left over; and the wafer is cut into at least one chip, thereby completing wafer level chip size package. The steps improve package reliability.
Description
technical field [0001] The invention relates to the field of semiconductor device packaging, in particular to a wafer level chip scale packaging (WaferLevel chip Scale Package, WLCSP) method. Background technique [0002] In recent years, since the microcircuit manufacturing of chips is developing toward high integration, the chip packaging also needs to develop in the direction of high power, high density, thinness and miniaturization. Chip packaging means that after the chip is manufactured, the chip is wrapped in plastic or ceramic materials to protect the chip from external moisture and mechanical damage. The main functions of the chip package are power distribution, signal distribution, heat dissipation and protection support. [0003] Since today's electronic products are required to be light, thin, small and highly integrated, the fabrication of integrated circuits will be miniaturized, resulting in an increase in the number of logic circuits contained in the chip, w...
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Login to View More IPC IPC(8): H01L21/50H01L21/60
CPCH01L24/11H01L2224/11H01L2924/01322H01L2924/14H01L2924/00H01L2924/00012
Inventor 王津洲
Owner SEMICON MFG INT (SHANGHAI) CORP