Simulation control method and system for programmable logic device

Abstract

The invention discloses a simulation control method for a programmable logic apparatus and a system. The invention conducts an external clock source model and directly connects the model to a trigger in a simulated circuit. As the external clock source model on which a simulation application procedure is based to carry out simulation is directly connected to the trigger of the simulated circuit without passing through any other standard units, the bypass of an external clock signal in the simulated circuit is led to reach the actual transmission paths of the clock signals of each trigger, thereby being capable of ensuring the external clock signal to synchronously reach each trigger; besides, as the transmission paths to reach the external clock signals of each trigger are the same, the simulation application procedure is arranged in that the external clock signals reaching to the triggers are synchronous when sampling the simulation triggers, thereby matching with the data output andsampling time between cascaded triggers and then avoiding the data from being mistakenly collected.

Description

technical field [0001] The invention relates to control technology, in particular to a simulation control method of a programmable logic device and a simulation control system of a programmable logic device. Background technique [0002] Programmable logic devices can implement various circuit structures. In order to ensure the feasibility and reliability of circuit structures based on programmable logic devices, it is usually necessary to use simulation applications to simulate them. [0003] Specifically, after inputting the code representing the simulated circuit into the simulation application program for synthesis, the netlist of the simulated circuit before layout and routing can be obtained; then, the simulation application program can perform simulation on the netlist of the simulated circuit . [0004] The netlist of the simulated circuit is composed of various standard cells, which respectively represent logic components such as D flip-flops (DFF), AND gates, NOT ...

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Problems solved by technology

[0016] It can be seen that in the existing simulation process, regardless of whether the real delay of the clock signal is 0 or not, the simulation application program will set the clock signals of different transmission paths to be asynchronous when the simulation flip-flop is sampled, so that the cascaded flip-flops in the simulated circuit The data output during the interval does not match the sampling timing, which may lead to wrong data collection

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