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System bus deadlock prevention method, device and on-chip system

A system bus, system deadlock technology, applied in the direction of instruments, electrical digital data processing, etc., can solve problems such as limiting the processing speed of Master1, unable to access Slave1 normally, and no processing, to ensure performance, reduce blocking time, and ensure processing. effect of speed

Active Publication Date: 2008-11-19
HONOR DEVICE CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0013] 2. If two Masters use the same ID number to access different Slaves at the same time, it will block the operation of the latter Master
The id0 operation sent by Master2 to Slave2 may be blocked for a long time in Slave2, making Master1 blocked for a long time, so the processing speed of Master1 is severely limited here.
[0016] The second anti-deadlock method may also have the following defects: Figure 4 As shown, Master2 first sends the operation of id0 to Slave2, and then sends the operation of id0 to Slave1. Because of the priority, Slave2 has not processed the operation of id0 sent by Master2 for the time being, and Slave1 has already processed the operation of id0 sent by Master2. operation, however, it is necessary to wait until the data of Slave2 is returned to Master2 before returning the data of Slave1 to Master2
Cause other Masters, such as Master1 and Master0, cannot access Slave1 normally

Method used

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  • System bus deadlock prevention method, device and on-chip system
  • System bus deadlock prevention method, device and on-chip system
  • System bus deadlock prevention method, device and on-chip system

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Embodiment 1

[0052] Such as Figure 5 As shown, the anti-deadlock method of the system bus in this embodiment includes the following steps:

[0053] 501. The bus interconnection module receives an operation command sent by the master device. In this embodiment, the operation command may include a serial number, an accessed slave device, an address corresponding to the operation command, and a specific operation of the operation command.

[0054] 502. The bus interconnection module judges whether the received operation command and the delivered but unfinished target operation command will cause a system deadlock. The specific technique for judging whether it will cause system deadlock in this step is: when the same master device uses the same serial number operation command to access different slave devices, or different master devices use the same serial number operation command to access different slave devices respectively When the device is used, it may cause system deadlock when the s...

Embodiment 2

[0066] This embodiment is an anti-deadlock technology of the internal bus of the system implemented in the AXI bus, and a similar technical solution of this embodiment can also be adopted in other buses. Such as Figure 8 As shown, the anti-deadlock method of the system bus in this embodiment includes the following steps:

[0067] 801. The interconnect of the AXI bus saves each operation command sent to the slave device, and records the serial number of the saved operation command and the corresponding slave device. After the operation command is completed, it can be invalidated, or directly To delete, in this embodiment, the method of setting to invalid is adopted. The effective target operation command saved in the interconnect indicates that the operation command has been sent but not completed.

[0068] 802, the interconnect of the AXI bus receives the operation command sent by Master1 (master device 1), assuming that the sequence number of the operation command is 0, th...

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Abstract

An embodiment of the invention discloses an anti-deadlock method, a device and an on-chip system of a system bus and relates to the on-chip system technical field to solve the problem that the existing deadlock prevention technology can affect the performance of the system bus to a greater extent. The embodiment of the invention blocks the operations which can possibly cause deadlock, and by sending a priority improving command, the embodiment helps the equipment to speed up the processing speed of the previously sent operation command which causes deadlock root. The embodiment of the invention is mainly used in the bus-required systems or equipment, such as AXI system bus.

Description

technical field [0001] The invention relates to the technical field of system bus, in particular to a method and device for preventing deadlock of interconnection bus inside a system on a chip, and a system on a chip. Background technique [0002] The interconnection protocols of the internal bus of the relatively mature SoC (SoC, System on Chip, System on Chip) include AXI (Advanced Extensible Interface), OCP (Open Core Protocol) and so on. In the SoC architecture based on the AXI bus protocol, the data flow exchange between multiple Masters (master devices) and multiple Slaves (slave devices) is realized through the Bus Matrix (bus matrix) of the Interconnect (bus interconnection module). The AXI protocol tracks the data through the ID number carried by the data. The Interconnect of AXI judges the destination exit according to the address control signal, but the data is transmitted sequentially according to the serial number it carries, that is, the data of the same ID num...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/14G06F13/40
Inventor 曾华夏晶
Owner HONOR DEVICE CO LTD
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