Semiconductor device and method for manufacturing same
A device manufacturing method and semiconductor technology, which are applied in semiconductor/solid-state device manufacturing, semiconductor devices, transistors, etc., can solve problems such as weak gate wiring resistance effect and inability to obtain transistor performance characteristics.
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Embodiment 1
[0148] The exemplary embodiment is NiSi 2 An example where the phase is formed on the lower part of the gate electrode and the NiSi phase is formed on the upper part. image 3 (a) to (e) and Figure 4 (f) to (1) show cross-sectional views of the MOSFET manufacturing process related to this exemplary embodiment.
[0149] First of all, such as image 3 As shown in (a), the element isolation region 2 is formed in the surface area of the silicon substrate 1 by using the STI (Shallow Trench Isolation) technology. Then, a gate insulating film 3 (3a and 3b) is formed over the surface of the element isolation silicon substrate. The gate insulating film has a structure including a silicon oxide film 3a and a high dielectric constant insulating film 3b. This exemplary embodiment uses HfSiO 2 And SiO 2 The composition of the gate insulating film, in which the Hf concentration in the gate insulating film changes in the depth direction, the Hf concentration is highest near the interface betw...
Embodiment 2
[0165] This is to form Ni under the gate electrode 3 Examples of Si phase and NiSi phase formed on top. Figure 5 (a) to (f) and Figure 6 (g) to (1) show cross-sectional views of the MOSFET manufacturing process related to this exemplary embodiment.
[0166] First of all, such as Figure 5 As shown in (a), by proceeding with the above reference image 3 (a) to (e) describe a similar process to Exemplary Embodiment 1 to expose the upper surface of the polysilicon film 10 for gate use.
[0167] Then, the height of the polysilicon film 10 is reduced to half of the interlayer insulating film 11 or less by dry etching ( Figure 5 (b)). This is because Ni is formed by full silicidation technology 3 The Si layer causes volume expansion due to silicidation, which makes Ni 3 The height of the Si layer is double or even higher than that of the polysilicon film 10 before silicidation. If the height of the polysilicon film 10 is set to be approximately equal to the interlayer insulating film...
Embodiment 3
[0182] This is the use of NiSi in the gate electrode of the N-type MOSFET 2 Phase and form Ni in the gate electrode of P-type MOSFET 3 Examples of Si phases. Figure 7 to Figure 11 A cross-sectional view of the MOSFET manufacturing process related to this exemplary embodiment is shown.
[0183] First of all, such as Figure 7 As shown in (a), by proceeding with the above reference image 3 (a) to (e) describe a similar process to Exemplary Embodiment 1 to expose the upper surface of the polysilicon film 10 for gate use.
[0184] Next, the diffusion prevention layer 20 is deposited entirely over the wafer where the upper surface of the polysilicon film 10 is exposed. This diffusion prevention layer 20 is intended to prevent the metal of the first metal film 19 for forming the silicide electrode of the N-type MOSFET from diffusing into the polysilicon film in the P-type MOSFET region. For this diffusion prevention layer 20, it is required that it can prevent the metal 19 for silicida...
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