Asymmetrical field-effect semiconductor device with STI region

Abstract

A high voltage asymmetric semiconductor device (20) that includes a shallow trench isolation (STI) region (22) that forms a dielectric between a drain (34) and a gate (36) to allow for high voltage operation, wherein the STI region includes a lower corner (24) that is shaped, e.g. rounded, to reduce an impact ionization rate. Exemplarity the shaped corner terminates on a (111) crystalline plane facet.

Description

technical field [0001] The present invention relates generally to semiconductor device structures, and more particularly to a semiconductor device structure having a shallow trench isolation (STI) region forming a dielectric between a drain and a gate, wherein the bottom corners of the STI region are rounded. Background technique [0002] Asymmetric semiconductor devices contain shallow trench isolation (STI) regions inside the cell, and all on-current must flow under the bottom corners of the STI, leaving the surface drain. STI regions are typically formed in trenches defined by two corners of approximately 90 degrees. Unfortunately, because the current must flow under the trench, the sharp corners cause high electric fields, which reduce the robustness of the device. Accordingly, there is a need for an asymmetric semiconductor device including an optimally shaped STI region. Contents of the invention [0003] The invention addresses the above-referenced problems, as we...

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Problems solved by technology

Unfortunately, because the current must flow under the trench, the sharp corners cause high electric fields, which reduce the robustness of the device

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