Electro-static discharging protection circuit

Abstract

The invention relates to a static discharge protecting circuit which is connected between a positive voltage source and a joint pad. The static discharge protecting circuit comprises a row of equidirectional and serial diodes, a resistor and a transistor, wherein an anode and a cathode are arranged at two ends of each diode, and the cathode is connected with the joint pad; the resistor is connected between the positive voltage source and the anodes of the serial diodes; a grid pole and a source pole of the transistor are connected to the positive voltage source, a drain pole of the transistor is connected to the joint pad, and a basal pole of the transistor is connected to the anode of the serial diode. Compared with the prior art, the invention has simple circuit structure, lower and adjustable trigger voltage and more effective static discharge protecting property.

Description

technical field [0001] The invention relates to an electrostatic discharge protection circuit. Background technique [0002] In complementary metal oxide field effect semiconductor (MOSFET) integrated circuits, the phenomenon of electrostatic discharge (Electrostatic Discharge) has attracted widespread attention. Among various electrostatic discharge protection devices, Gated MOSFET is favored by designers because of its better protection ability and simpler design. figure 1 It is a schematic diagram of a circuit using a Gated MOSFET as an ESD protection device, wherein the ESD protection circuit at the output end can be replaced by the output buffer of the circuit itself. by figure 1 The electrostatic discharge protection circuit shown is an example. When performing an electrostatic discharge test, the test combination PS (that is, the bonding pad 5 is connected to the forward voltage, VSS6 is grounded, and the other junction pins are suspended) and ND (that is, the bondi...

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Problems solved by technology

by figure 1 The electrostatic discharge protection circuit shown is an example. When performing an electrostatic discharge test, the test combination PS (that is, the bonding pad 5 is connected to the forward voltage, VSS6 is grounded, and the other junction pins are suspended) and ND (that is, the bonding pad 5 connected to the negative voltage, the positive voltage source VDD4 is grounded, and the electrostatic discharge test method in which the other nodes are suspended) the electrostatic discharge protection voltage obtained is low, which limits the electrostatic discharge protection capability of the entire circuit system (chip)

This is because in the PS test mode, the device that plays the main role of electrostatic discharge protection is Gated NMOS, which mainly uses parasitic triodes to guide the large current generated by electrostatic discharge, and its trigger voltage value (trigger voltage) is about N+ The reverse breakdown voltage value of / P well diode, and this value is limited by different process flow

Similarly, in the ND test mode, the trigger voltage of the electrostatic discharge protection device Gated PMOS is also limited by different process flows

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