Bolt lock device

Abstract

A latching device comprises an amplification circuit, a latching unit and a bias circuit. The amplification circuit is used for receiving a first bias current in a first state, so as to amplify an input signal and produce an amplified signal; the latching unit is used for latching the amplified signal and receiving a second bias current in a second state, so as to output the amplified signal; thebias circuit is used for supplying the first bias current to the amplification circuit, and supplying the second bias current to the latching unit; and the bias circuit comprises a first bias module used for supplying a third bias current to the amplification circuit in the first state, and a second bias module used for supplying a fourth bias current to the amplification circuit in the first state, wherein, the first bias current equals to the sum of the third bias current and the fourth bias current.

Description

Technical field [0001] The invention relates to a latch, in particular to a latch capable of high-frequency operation. Background technique [0002] In integrated circuits, clock signals of different frequencies are often used to perform different operations; therefore, phase locked loop / synthesizers are widely used in the industry to produce different Frequency clock signal. [0003] As existing in the industry, the phase-locked loop / frequency synthesizer has a divider to divide the signal generated by its internal voltage-controlled oscillator, so that the feedback mechanism of the divider can be used to make The output of the phase-locked loop can generate a signal of the required frequency. [0004] Generally speaking, the frequency divider is usually implemented using D-type flip flops. See here figure 1 , figure 1 It is a schematic diagram of the existing frequency divider 100 with a divisor of 2. Such as figure 1 As shown, the frequency divider 100 is implemented by a D-ty...

AI Technical Summary

Problems solved by technology

[0010] First of all, the first method is to increase the current without adjusting the aspect ratio (W / L ratio) of the internal transistor of the bias module, but this method will make the gate of the bias current source (usually a current mirror circuit) Drain voltage V DS Smaller, it may even cause the bias current source to enter the triode region (triode region), so that the current cannot be increased, and the operating frequency cannot be increased

[0011] The second method is to increase the current and adjust the aspect ratio of the internal transistor accordingly; however, this method will increase the parasitic capacitance seen from the gate terminal of the internal transistor; For a flip-flop, the added parasitic capacitance will be the load of the previous D-type flip-flop

In other words, the increased parasitic capacitance of the next-stage D-type flip-flop will increase the RC delay of the previous-stage D-type flip-flop, thereby limiting the maximum operating frequency of the overall circuit

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