High-speed SAR ADC circuit

Abstract

The invention discloses a high-speed SAR ADC circuit, which comprises a capacitor DAC array, a comparator, an REF circuit, a clock logic circuit and a data logic circuit, and is characterized in that the REF circuit is connected with the capacitor DAC array; the capacitor DAC array is connected with two input ends of the comparator; the comparator is connected with the clock logic circuit and the data logic circuit; the clock logic circuit outputs a comparator clock to the comparator; the data logic circuit outputs a DAC control signal to the capacitor DAC array; according to the data logic circuit, an additional M-bit DFF unit is added on the basis of an N-bit DFF unit, meanwhile, an additional M-bit data processing unit is added on the basis of an N-bit data processing unit, and both N and M are positive integers. According to the invention, by automatically adjusting the circuit delay and the current of the reference voltage circuit, the speed and the performance of the asynchronous SAR ADC can be kept stable under PVT, and the power consumption is reduced.

Description

technical field [0001] The present invention relates to successive approximation (SAR) analog-to-digital converters (ADCs). Background technique [0002] Successive approximation analog-to-digital converters have been widely used due to their low power consumption and low delay. However, due to the characteristics of successive approximation, SAR ADC with N bit resolution needs at least N conversion cycles, so the speed is relatively slow. Although the SAR ADC with asynchronous timing has improved in speed, in the actual design, the total time of N conversion cycles varies greatly with the PVT (Process, Voltage, Temperature, process-voltage-temperature) corner (process angle), The speed is easily doubled under the fastest and slowest PVTCorner. In traditional design, the driving capability of the delay unit and the reference level drive circuit is set under the slowest Corner, so that Typical (standard process corner) and faster The reference level driving circuit of the co...

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Problems solved by technology

[0002] The successive approximation analog-to-digital converter has been widely used due to its low power consumption and low delay. However, due to the successive approximation, the SAR ADC with N bit resolution needs at least N conversion cycles, so the speed is slow

Although the SAR ADC with asynchronous timing has improved in speed, in the actual design, the total time of N conversion cycles varies greatly with the PVT (Process, Voltage, Temperature, process-voltage-temperature) corner (process angle), The speed is easily doubled under the fastest and slowest PVTCorner. In traditional design, the driving capability of the delay unit and the reference level drive circuit is set under the slowest Corner, so that Typical (standard process corner) and faster The reference level drive circuit of the corner is over-designed, resulting in a large power consumption of the SAR ADC

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