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AEDF task scheduling method based on SMP

A task scheduling and task technology, applied in the direction of resource allocation, multi-programming devices, etc., can solve the problems of task allocation efficiency reduction, etc., to achieve the effect of improving execution priority, improving utilization rate, and improving execution efficiency

Inactive Publication Date: 2009-06-03
HARBIN ENG UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This scheduling method realizes the load balancing of each processor in the system; however, since the system shares a common queue, the system is required to ensure that each processor must mutually exclusive access to the ready queue, resulting in a reduction in task dispatching efficiency

Method used

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  • AEDF task scheduling method based on SMP
  • AEDF task scheduling method based on SMP

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Embodiment Construction

[0045] The present invention is described in more detail below in conjunction with accompanying drawing example:

[0046] Let the resource usage parameter table of each task be (period, time slice, deadline, running time, source cycle, source time slice, timing time of the next cycle, migration start time, relocation mark, privilege mark, migration time limit) , tasks are classified according to their status as ready tasks, privileged tasks, waiting tasks and blocked tasks. They are defined as follows:

[0047] Period: Indicates the relative cut-off time of the relative operation of the task. If the period is 20ms, it means that the task starts from the period timing and must stop running after 20ms;

[0048] Time slice: Indicates the maximum time that a task can run in a cycle;

[0049] Deadline: Indicates the deadline for the task to run within a cycle;

[0050] Running time: Indicates the time the task actually occupies the processor from the start of scheduling each tim...

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Abstract

The invention provides an AEDF task scheduling method based on an SMP, and designs a dynamic load balancing method which runs on the SMP and is based on self-adapting. The method can track the current load condition of all the processors in the SMP in real time, and reasonably allocates different tasks into the processor with less loads in a dynamic way; in the process of task scheduling, by counting the runtime of the hung task, the method regulates time slot, period and blocking time of the next time of running in a dynamic way. The AEDF task scheduling method based on the SMP can comprehensively analyze the current load condition of the processors, task-fulfilling situation and the running condition of the system, and reasonably allocates resources of the processors, thus effectively improving the utilization rate of the resources of all the processors in the SMP, shortening execution time needed by completing all the tasks, and leading the operating efficiency and the using effectiveness of the SMP to be effectively improved; meanwhile, by adopting the execution sequence of dynamic scheduling task resources, the real-time requirements for executing urgent task can be guaranteed in a preferential way.

Description

(1) Technical field [0001] The invention relates to a method for improving computer processing speed, in particular to a processor task scheduling method in computer SMP architecture. (2) Background technology [0002] Multi-processor technology is an effective technology to increase the speed of computer operation. It solves complex problems cooperatively through multi-task parallel operations to improve computer performance; at the same time, this technology can use redundant processors to realize system reconfiguration to improve System reliability and availability. [0003] Symmetric multiprocessor architecture (SMP: Sy mmetric M ulti- P processor) is a typical multiprocessor architecture applied to enterprise servers. SMP is a computer architecture that consists of two or more connected processors that cooperate to process the same set of tasks. Usually, identical processors are used in SMP, and each processor has an exclusive high-speed cache (Cache), and each pro...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/50
Inventor 姚文斌郑兴杰王帅元司艳芳
Owner HARBIN ENG UNIV
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