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Data transmission rate regulation for serial interface large-capacity storage apparatus

A data transmission and rate adjustment technology, applied in the direction of electrical digital data processing, instruments, input/output to record carriers, etc., can solve the problems of low efficiency of flow control and will not improve the effective transmission rate, etc.

Inactive Publication Date: 2009-06-24
NVIDIA CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Flow control introduces inefficiencies because each transfer between the Serial ATA storage device and the host device incurs several cycles of latency (limited to a specified maximum) due to round-trip handshaking across the Serial ATA interface
Simply increasing the size of the data FIFO to store more incoming data can be used to delay the first occurrence of the flow control sequence, but will not improve the effective transfer rate once the data FIFO has been filled in the first place

Method used

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  • Data transmission rate regulation for serial interface large-capacity storage apparatus
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Embodiment Construction

[0014] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described herein in order to avoid obscuring the present invention.

[0015] The present invention relates to new systems and methods for improving the effective data transfer rate of Serial ATA storage devices. Effective data transfer rate is reduced by inserting alignment primitives when sending data. The receiving device simply discards the alignment primitive. Therefore, the receive data FIFO does not fill quickly and flow control requires less R_IP to hold to hold A to R_IP sequences. The alignment primitive has the advantage of not incurring round-trip handshake delays to disable and then enable data transfers. In cont...

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Abstract

The invention discloses a system and a method for executing data transferring rate adjustment to improve the effective data transfer rate of a serial ATA storage apparatus. When the data is transferred, the insertion of an ALIGN primitive element reduces the data transferring rate. A receiving device only abandons the ALIGN primitive element. Thus a receiving data First-In First-Out (FIFO) is not filled in and a flow control sequence with less flow control demand prevents the data FIFO from overflow. The advantage of the ALIGN primitive element instead of the conventional flow control is that the ALIGN does not cause a roundtrip signal switching delay and discontinuation and later starts the data transfer.

Description

technical field [0001] One or more aspects of this disclosure generally relate to serial data transfers using the Serial ATA (SATA) protocol, and more particularly, to regulating data transfer rates to minimize the use of hold primitives for flow control. Background technique [0002] The Serial ATA Disk Access Protocol is used to transfer data between system memory and one or more disks. Most Serial ATA storage devices have very limited data transfer throughput compared to system memory bandwidth. Sustained write throughput can be as low as 100MB / sec for tape-based drives. Consequently, these Serial ATA storage devices can become a performance bottleneck when coupled to fast host processors that can sustain transfer rates of 300MB / sec (as described by the Serial ATA specification). [0003] The Serial ATA protocol specifies a flow control mechanism to regulate the data transfer rate. In particular, the transfer of data from the host processor to the Serial ATA storage de...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F3/06G06F13/38
CPCG06F13/385G06F13/42G06F13/40G06F13/14
Inventor 安布杰·库马尔马克·A·奥弗比
Owner NVIDIA CORP
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