CDR circuit
A circuit and circuit reading technology, which is applied in the field of CDR circuits, can solve the problem of jitter in restored data, and achieve the effect of solving jitter
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Method used
Image
Examples
no. 1 example
[0030] figure 1 The configuration of the CDR circuit 100A according to the first embodiment of the present invention is shown. reference figure 1 , Reference numeral 101 represents FIFO (First In First Out) 102 represents VCO; 103 represents frequency comparator; 120 represents input data; 121 represents recovered data; 122 represents reference clock. The VCO 102 and the frequency comparator 103 form a PLL (Phase Locked Loop) circuit and a recovered clock generation circuit. The FIFO 101 forms a data write / read circuit.
[0031] The frequency of the reference clock 122 is the same as the data rate frequency of the input data 120. The frequency comparator 103 compares the frequency of the reference clock 122 with the output clock (recovered clock) 123 from the VCO 102. For example, the frequency comparator 103 compares the number obtained by counting the reference clock 122 every predetermined time with the number obtained by counting the recovered clock 123 from the VCO 102 e...
no. 2 example
[0035] figure 2 The configuration of the CDR circuit 100B according to the second embodiment of the present invention is shown. in figure 2 Middle, used with figure 1 The same reference numerals used refer to figure 1 The same constituent elements in. In this embodiment, dividers 104 and 105 are inserted figure 1 The two input sides of the frequency comparator 103 in the CDR circuit 100A are shown. The phase comparator 106 and the VCO 107 are newly added to form a PLL circuit. The frequency dividers 108 and 109 are also inserted into the two input sides of the phase comparator 106. Reference numerals 125 and 126 denote reference clocks.
[0036] In order to generate the recovered clock 123 for writing to the FIFO 101, the reference clock 125 is used. Let f2 represent the frequency of the reference clock 125, f1 represent the frequency of the write clock of the FIFO 101, n1 represent the frequency division ratio of the frequency divider 104, and n2 represent the frequency ...
no. 3 example
[0045] image 3 The configuration of the CDR circuit 100C according to the third embodiment of the present invention is shown. in image 3 Middle, used with figure 1 The same reference numerals used refer to figure 1 The same constituent elements in. Reference numeral 110 denotes a phase comparator 111 denotes a VCO. The VCO 102, the phase comparator 110, and the VCO 111 form a recovered clock generation circuit.
[0046] The phase comparator 110 compares the phase of the output clock from the VCO 111 with the phase of the reference clock 122. The signal 129 representing the comparison result is input to the VCO 111 as a frequency control signal, and the signal 129 is also input to the VCO 102 as a frequency control signal.
[0047] In this embodiment, since the VCO 111 is used, the conventional phase comparator 110 can be used instead figure 1 The frequency comparator 103 in the CDR circuit 100A is shown. The working mode of this embodiment is the same as figure 1 The CDR c...
PUM
Login to View More Abstract
Description
Claims
Application Information
Login to View More