Processor system and its access method

Abstract

The invention discloses a processor system and a memory access method thereof. The system comprises an I / O (input / output) bus, at least a multi-core processor, and an I / O controller. The multi-core processors adopt a two-dimensional grid as a basic interconnection topology structure; the multi-core processors are connected through the I / O bus; each node in the two-dimensional grid comprises a crossbar switch, a main device, and an auxiliary device; wherein, the crossbar switch is used for connecting the main device and the auxiliary device, as well as communicating with the crossbar switches of adjacent nodes in the two-dimensional grid, so as to carry out data transmission among cores of the processor; the main device is used for initiatively sending read and write requests to the auxiliary device through the connection with the crossbar switch; the auxiliary device is used for receiving the requests of the main device and conducting data or state responses through the connection with the crossbar switch; and the I / O controller is connected with the boundary nodes of the two-dimensional grid and used for realizing data transmission among the multi-core processors.

Description

technical field [0001] The present invention relates to the field of processors, in particular to the field of processor systems composed of multi-core processors. More specifically, the present invention relates to a processor system and a memory access method thereof. Background technique [0002] A multi-core processor refers to a processor architecture that integrates multiple microprocessor cores on a single chip, which can execute program codes in parallel, reduce the power consumption of the processor without increasing the operating frequency of the processor, and obtain high polymerization performance. In this kind of processor, the interconnection structure is the core of the chip. Modules such as the processor core, level 2 cache (Cache) and input / output (I / O) are connected through the interconnection structure to form a complete chip, and through the interconnection structure Complete the transmission and exchange of data information, so the design of the interc...

AI Technical Summary

Problems solved by technology

Third, after entering the nanoscale process, the delay of the interconnect line replaces the delay of the gate and becomes the main factor that dominates the delay of the chip, resulting in an increase in the global data communication delay between modules.

[0004] Under the influence of the above factors, traditional interconnection methods such as buses, crossbars, and 2D grids (MESH) are difficult to meet the requirements of multi-core processors for scalability and efficiency.

For example, the bus structure needs to implement a global arbitration mechanism, which is difficult to overcome the influence of line delay. At the same time, multiple modules sharing the bus will affect scalability and efficiency.

Although the crossbar switch can avoid the realization of global arbitration, its resource consumption (including wiring, buffers, etc.) has a quadratic relationship with the number of connected modules, and it does not have good scalability.

The 2-dimensional MESH structure is a distributed control structure. Although it can overcome the disadvantages of the bus and the crossbar switch and has certain scalability, it needs to implement a more complex routing control mechanism.

[0005] The Chinese invention patent with the application number of 200810062164.1 discloses a method for realizing the organization level of on-chip communication and interconnection of embedded heterogeneous multi-core system. Compared with the present invention, it is only applicable to the on-chip communication and interconnection of embedded heterogeneous multi-core. Certain limitations; and it uses bus interconnection, which restricts the scalability of multi-core processors

The Chinese invention patent with the application number of 200710103959.8 discloses a multiprocessor system. Compared with the present invention, although it also utilizes a crossbar switch, it does not implement a shared secondary cache, which increases the overhead in routing implementation. The communication efficiency is low, and it also restricts the scalability of multi-core processors

Images