Instruction combination filtration method and system for instruction grade stochastic verification

A technology of instruction combination and random verification, applied in special data processing applications, instruments, electrical digital data processing, etc., can solve problems such as error debugging process, repeated coverage, etc.

Active Publication Date: 2010-12-08
LOONGSON TECH CORP
View PDF1 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0014] In order to solve the above-mentioned technical problems, a method and system for instruction combination filtering for instruction-level random verification are provided. The practical needs of complex integrated circuit verification such as the debugging process and avoiding repeated coverage of test vectors to verify design function points

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Instruction combination filtration method and system for instruction grade stochastic verification
  • Instruction combination filtration method and system for instruction grade stochastic verification
  • Instruction combination filtration method and system for instruction grade stochastic verification

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0048] The instruction combination filtering method for instruction-level random verification of the present invention is realized through the following technical solutions, specifically including:

[0049] Step 1, add constraints related to the instruction combination to be filtered in the instruction template, including the number of instruction combinations allowed to be filtered, the maximum length of the instruction combination, and the type definition of the instruction combination;

[0050] Step 2, redesign the instruction filter to queue mode, and the length of the queue is the maximum length of the instruction combination allowed to be filtered defined in the instruction template in step 1;

[0051] Step 3, adding counting logic and queue head and tail indicators to the command filter;

[0052] Step 4, adding comparison logic of single and multiple instruction combinations in the instruction filter;

[0053] Step 5, redesign the entry, output and filtering mechanism ...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

The invention relates to an instruction combination filtering method and a system thereof which are used for instruction-level random verification. The method comprises the following steps: step 1, relevant constraints of the instruction combination to be filtered are added to instruction templates and the constraints comprise type definition of the instruction combination; step 2, the instruction filter is set to be in the FIFO queue mode; step 3, if the instruction combination entering the filter instruction queue is matched with the constraints, the instruction first entering the instruction queue of the instruction filter is deleted; otherwise, the instruction first entering the instruction queue of the instruction filter is output. The invention has the advantages of effectively solving the problem of flexible instruction combination filtering in random verification of large scale integrated circuits, meeting requirement of the debugging process with simplification design errors during verification of complex integrated circuits, preventing the test vectors from repeatedly covering design function points to be verified and the like, thereby better supporting the verification of complex integrated circuits.

Description

technical field [0001] The invention relates to the field of VLSI design verification, in particular to an instruction combination filtering method and system for instruction-level random verification. Background technique [0002] Functional verification is considered to be the bottleneck in the current hardware design process. In fact, in the entire design process, about 70% of the time and resources are spent on functional verification. Finding as many errors as possible has always been the focus of attention in the field of verification. [0003] Functional verification methods are mainly divided into two categories: simulation methods and formal methods. The application of formal methods is largely limited by the design scale; while simulation methods can handle large-scale integrated circuit design, especially contemporary complex high-performance processors, and are currently the main method for processor function verification. There are three main sources of the la...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
Patent Type & Authority Patents(China)
IPC IPC(8): G06F17/50
Inventor 沈海华王朋宇张珩
Owner LOONGSON TECH CORP
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products