Boundary scanning chip failure detection device and method

A fault detection and boundary scan technology, applied in measurement devices, measurement of electricity, measurement of electrical variables, etc., can solve the problems of inaccurate fault location and difficult detection, and achieve the effect of improving work efficiency

Inactive Publication Date: 2009-09-09
MITAC COMP (SHUN DE) LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] The purpose of the present invention is to propose a boundary scan chip fault detection device and method that facilitates fault location and improves motherboard maintenance efficiency, and solves the problems of difficult detection and inaccurate fault location

Method used

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  • Boundary scanning chip failure detection device and method
  • Boundary scanning chip failure detection device and method
  • Boundary scanning chip failure detection device and method

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Embodiment Construction

[0028] Embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

[0029] The function realization of the present invention mainly controls the resident program in the microprocessor on the JTAG (Joint TextAction Group) conversion module to complete the reading and writing of the test vector through the user operation application program, and the microprocessor generates the JTAG test interface drive signal to drive the JTAG bus , and finally the application program analyzes and diagnoses the test results and uses relevant information files to locate the fault point.

[0030] figure 1 It is a schematic flow chart of the boundary scan chip fault detection method of the present invention. As shown in the figure, a boundary scan chip fault detection method uses an application program to connect to the test interface of the chip under test 20 to perform comprehensive detection on the chip under test 20;

[0031] The conc...

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Abstract

The invention discloses a boundary scanning chip failure detection device and a method. A test interface connected to a detected chip by an application program fully detects the detected chip. The device comprises an application program module, a receiving and analyzing feedback information unit and a display module, wherein the application program module is provided with a vector sending unit which can send a test vector to the detected chip and detect a detected main board; the receiving and analyzing feedback information unit receives the feedback information of the detected chip and acquires the detection results through analyzing the feedback information; and the display module displays the detection results acquired by analyzing the feedback information through the application program module. The method comprises the following steps: a, sending the test vector to the detected chip; b, receiving and analyzing the feedback information of the detected chip; and c, displaying the detection results acquired by analyzing the feedback information. The device and the method achieve full detection of the detected chip, and can successfully detect question points of the detected chip and accurately position; and the test is more convenient.

Description

technical field [0001] The present invention relates to a fault detection device and method, in particular to a boundary scan chip fault detection device and method. Background technique [0002] The detection of faults on the circuit board is usually carried out by using traditional detection equipment such as probes and needle beds. With the development of integrated circuits into the era of VLSI, the high complexity of circuit boards and multi-layer printed boards, surface mount (SMT), ball grid array (BGA), wafer scale integration (WSI) and multi-chip modules The application of (MCM) technology in the circuit system makes the physical accessibility of circuit nodes gradually weakened or even disappears, and the testability of circuits and systems drops sharply. Due to the increasing integration of the circuit board, the distance between the nodes available for testing is getting smaller and smaller, and some even completely become recessive nodes. There are many disadv...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G01R31/28G01R31/3185
Inventor 刘占锋
Owner MITAC COMP (SHUN DE) LTD
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