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Parallel LU decomposition for corner sparse matrix based on FPGA

A sparse matrix and decomposer technology, applied in the field of data processing, can solve the problems of poor stability, low execution efficiency, slow execution speed, etc., to reduce system cost, improve data speed, and facilitate porting.

Inactive Publication Date: 2009-09-16
XIDIAN UNIV
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  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The implementation of NIOS core programming using FPGA has great flexibility, but the execution efficiency is low, the execution speed is slow and the stability is poor.

Method used

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  • Parallel LU decomposition for corner sparse matrix based on FPGA
  • Parallel LU decomposition for corner sparse matrix based on FPGA
  • Parallel LU decomposition for corner sparse matrix based on FPGA

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Embodiment Construction

[0015] The present invention will be described in detail below in conjunction with the accompanying drawings and examples.

[0016] refer to figure 1 , the present invention implements a corner block sparse matrix parallel LU decomposer based on FPGA. The decomposer consists of an analog sorting module, a symbolic decomposing module and a parallel numerical LU decomposing module to form a general processing platform structure. in:

[0017] The analog sorting module, as the input module of the whole system data, determines the elimination order for the symbolic decomposition of the corner block sparse matrix and determines the position of the filling element, which is located at the front end of the whole device; The original data has been recombined. For example: a fourth-order sparse matrix of corner blocks is originally eliminated in order from the first row to the first column, until the end of the fourth row and fourth column, and the order is eliminated after the simul...

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Abstract

Aiming at the characteristics that corner-block sparse matrix is capable of parallel computing, the invention provides a parallel LU decomposition for corner sparse matrix based on FPGA. a simulating-sorting module, a symbol resolution module and a parallel numerical LU decomposition module form a three-layer processing platform structure consisting of, wherein the parallel numerical LU decomposition module is used for executing the parallel LU decomposition to matrix data and is positioned at the tail end of a whole processing structure; the symbol decomposition module is used for marking the position of an element to be modified in the matrix and is positioned at the middle end of the whole processing structure; and the simulating-sorting algorithm module is used for determining the elimination order of the matrix and is positioned at the foremost end of the whole processing structure; and the three modules are connected through a shared memory unit. The decomposition has the advantage of executing parallel LU decomposition to the corner sparse matrix in real time, can greatly save development cost as compared with the prior art using parallel computers and distributed computers, and can be applied to the field of real-time electrical network analysis.

Description

technical field [0001] The invention belongs to the technical field of data processing, relates to a parallel LU decomposer, and is suitable for parallel LU decomposition of a bordered-diagonal-block sparse matrix (Bordered-Diagonal-Block). Background technique [0002] Corner block sparse matrix is ​​widely used in electronic network design, power system optimization design, graph theory and other science and technology and engineering fields. The solution of sparse linear equations is the core problem in many fields of science and technology. If it is necessary to solve the different right-hand vector b multiple times while the matrix A remains unchanged, the matrix LU decomposition method will significantly save computing time. And the matrix LU decomposition method can take advantage of the sparsity of the matrix and save a lot of storage space, so this method is suitable for solving large sparse matrix problems. [0003] At present, some supercomputers and distributed ...

Claims

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Application Information

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IPC IPC(8): G06F17/16H04L25/02H04B7/04H03K19/00
Inventor 石光明王亚南李甫张犁
Owner XIDIAN UNIV
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