Semiconductor element with auxiliary patterns and manufacture method thereof

Abstract

The invention discloses a semiconductor element with auxiliary patterns and a manufacture method thereof. The semiconductor element with auxiliary patterns comprises a substrate on which at least one active area and a peripheral area are defined. The semiconductor element also comprises a plurality of auxiliary patterns which can be arranged in the peripheral area of the substrate and also can be arranged in the active area by a figure in a broken line shape. Simultaneously, the auxiliary patterns can be respectively and electrically connected with an active circuit arranged in the active area, so that the active circuit can be used as a redundant circuit used for repairing or replacing a circuit with defects.

Description

technical field [0001] The invention relates to a semiconductor element and its manufacturing method, in particular to a semiconductor element with additional auxiliary patterns and its manufacturing method. Background technique [0002] With the development of integrated circuit manufacturing technology, the design dimensions of semiconductor devices are becoming more and more precise, and the problem of pattern width or thickness control is faced in the process. Therefore, reliable fabrication of deep submicron and smaller-sized features has become a key technology for the next generation of very large scale integration (VLSI) or ultra large scale integration (ULSI) semiconductor components. . For example, the ability to form reliable gate patterns at high device densities is critical to the successful construction of VLSI or ULSI. [0003] However, as the line width (critical dimension, CD) becomes smaller and smaller, when etching the gate pattern, not only the aspect ...

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Problems solved by technology

Simply put, the loading effect of the etching process between high and low density patterns often causes the etched gate pattern to lose the required uniformity, and at the same time affects the profile of the actual gate pattern, and the above two variations will eventually affect the gate pattern. The line width has an adverse effect on the

[0004] In addition, the uneven surface will also cause depressions during the subsequent global planarization

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