Failure testing system for embedded logic cores in system on chip

Abstract

The invention relates to a failure testing system for embedded logic cores in a system on chip, which is a circuit added for perfecting testability of the system on chip. The circuit thereof is composed of a testing access channel set, n testing loops, n logic core testing control units, a logic core testing control bus and a logic core testing selection control unit, wherein n is number of the logic cores in the system on chip. The invention can comprehensively test and access each deeply embedded logic core in the system on chip, and can guarantee mutual separation and effective control of each logic core in testing process. The circuit has simple structure and is applied to various systems on chip constructed by using embedded logic core design method.

Description

technical field [0001] The invention relates to a fault testing system for an integrated circuit, in particular to a fault testing system which can be repeatedly applied to a SOC System on a Chip (SOCSystem on a Chip) integrated circuit. Background technique [0002] Advanced semiconductor processing and design techniques have greatly increased the likelihood of successful integrated circuit design for complex systems. The traditional design method based on the standard cell library is gradually replaced by a design method using a larger-scale reusable logic core (IntellectualProperty Core). Due to the use of logic core reuse design methods, the design scale and implementation functions of integrated circuits have undergone a sudden change, from the original VLSI (Very Large Scale Integration Circuit) to the current system-on-chip. However, with the increasing design scale, increasing functional complexity and shortening design cycle of SoC, a serious problem is becoming mo...

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Problems solved by technology

However, it must be noted that this standard only has a relatively complete design definition for the function and behavior of the test ring, and only gives a framework definition for the test access channel and test controller, which has not yet been determined. Open to researchers from all over the world, it needs to be further improved by researchers from all over the world

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