Reading of a nonvolatile memory cell by taking account of the stored state of a neighboring memory cell
A non-volatile storage and memory technology, which is applied in the field of non-volatile storage devices, can solve the problems of increasing the coupling of adjacent floating gates by threshold voltage distribution, increasing the space between word lines and the coupling of adjacent floating gates, etc.
Active Publication Date: 2012-10-03
SANDISK TECH LLC
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Therefore, an increase in the threshold voltage distribution will exacerbate the coupling problem between adjacent floating gates
[0011] In addition, the reduction of the space between the word lines and the reduction of the space between the bit lines will also increase the coupling between adjacent floating gates.
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[0037]One example of a flash memory system uses a NAND structure that includes a series arrangement of multiple transistors sandwiched between two select gates. The series connection of transistors and the select gates is called a NAND string. figure 1 To show a top view of a NAND string. figure 2 as its equivalent circuit. figure 1 and figure 2 The NAND string depicted in includes four transistors 100 , 102 , 104 and 106 connected in series and sandwiched between a first (or drain) select gate 120 and a second (or source) select gate 122 . Select gate 120 connects the NAND string to the bit line via bit line contact 126 . Select gate 122 connects the NAND string to source line 128 . Select gate 120 is controlled by applying an appropriate voltage to select line SGD. Select gate 122 is controlled by applying an appropriate voltage to select line SGS. Each of transistors 100, 102, 104, and 106 has a control gate and a floating gate. For example, transistor 100 has a co...
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Shifts in the apparent charge stored on a floating gate (or other charge storage element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other charge storing elements). To account for this coupling, the read process for a targeted memory cell will provide compensation to an adjacent memory cell (or other memory cell) in order to reduce the coupling effect that the adjacent memory cell has on the targeted memory cell. The compensation applied is based on a condition of the adjacent memory cell. To apply the correct compensation, the read process will at least partially intermix read operations for the adjacent memory cell with read operations for the targeted memory cell.
Description
technical field [0001] The present invention relates to techniques for non-volatile memory devices. Background technique [0002] Semiconductor memory has become more and more commonly used in various electronic devices. For example, non-volatile semiconductor memory is used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices, and other devices. Electrically Erasable Programmable Read Only Memory (EEPROM) and flash memory are among the most common non-volatile semiconductor memories. [0003] Both EEPROM and flash memory utilize a floating gate positioned over and insulated from a channel region in a semiconductor substrate. The floating gate is positioned between a source region and a drain region. A control gate is provided over and insulated from the floating gate. The threshold voltage of a transistor is controlled by the amount of charge held on the floating gate. That is, the minimum amount o...
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IPC IPC(8): G11C16/34G11C11/56
CPCG11C16/3454G11C16/3418G11C29/52G11C16/04G11C16/26G11C16/0483G11C11/5642G11C16/3427G11C16/30G11C16/02
Inventor 尼玛·穆赫莱斯
Owner SANDISK TECH LLC