Method and apparatus for programmable delay having fine delay resolution

Abstract

An programmable delay apparatus includes a first delay stage having a delay cell which includes a passive network, where the first delay stage is capable of providing a first time delay. The apparatus further includes a second delay stage which includes a plurality of delay cells, where each delay cell is capable of providing a second time delay which is larger than the first time delay. A methodfor delaying an input signal includes receiving a delay select command based upon the desired time delay, establishing a circuit path which includes at least one delay element, selected from a plurality of delay cells, according to the delay select command, wherein at least one of the plurality of delay cells includes a delay element which comprises a passive network.

Description

[0001] This application claims priority to U.S. Provisional Application No. 60 / 939,288, filed May 21, 2007, entitled "PROGRAMMABLE DELAY METHOD AND APPARATUS," the entire disclosure of which It is considered part of the disclosure content of this application. technical field [0002] Embodiments of the present invention relate generally to time delay circuits and, more particularly, to circuits capable of providing programmable delays within an integrated circuit (IC). Background technique [0003] One challenge facing modern devices utilizing high speed synchronous communications is to properly align clock and data signals. Misalignment between such signals may reduce communication speed and / or potentially result in data corruption. As the commercial and technical demands for faster communications increase, the tolerances for misalignment become tighter, thus challenging designers to improve the performance of conventional techniques for maintaining precise alignment betwe...

AI Technical Summary

Problems solved by technology

Such devices may be limited to using only active components such as NAND logic, multiplexers, and / or inverters for their delay cells, and their delay resolution may be limited by a delay of 2 inverters or more, It can be 50ps×2=100ps in 65nm or 45nm CMOS manufacturing technology

To properly deskew high speed data and clock signals, 100ps resolution may not be sufficient

[0005] Conventional structures using differential circuits have been proposed to improve resolution; however, such implementations may require too much power and thus may not be suitable for use in battery-operated mobile devices such as mobile terminals

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