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Method for detecting frequency errors of sampling clock, device and system thereof

A sampling clock and frequency error technology, applied in the field of signal processing, can solve the problems of sampling clock frequency error, RAKE receiver implementation complexity, etc., and achieve the effect of moderate complexity

Inactive Publication Date: 2010-03-31
HUAWEI TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] RAKE receiver implementation is more complex, and when there is only one main path and small delay multipath, RAKE combination cannot solve the problem of sampling clock frequency error

Method used

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  • Method for detecting frequency errors of sampling clock, device and system thereof
  • Method for detecting frequency errors of sampling clock, device and system thereof
  • Method for detecting frequency errors of sampling clock, device and system thereof

Examples

Experimental program
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Effect test

Embodiment 1

[0045] See Image 6 It is a flowchart of a method for detecting a sampling clock frequency error in Embodiment 1 of the present invention, as Image 6 As shown, the embodiment of the present invention provides a method for detecting a sampling clock frequency error, including:

[0046] Step 601: According to the received two-period pseudo-random sequences, respectively calculate and obtain the partial channel impulse responses on the two-period pseudo-random sequences;

[0047] In one implementation, step 601 may include: correlating the received two-period pseudo-random sequences with known pseudo-random sequences, and calculating the channel impulse response on the two-period pseudo-random sequences;

[0048] From the channel impulse response of the pseudo-random sequence of these two periods, select the same main path, take M points on the left and right sides of the main path, M is a positive integer, and form two points with 2M+1 points respectively The partial channel ...

Embodiment 2

[0062] See Figure 7 It is a flowchart of a method for detecting a sampling clock frequency error in Embodiment 2 of the present invention, as Figure 7 As shown, the embodiment of the present invention provides a method for detecting a sampling clock frequency error, including:

[0063] Step 701: see Figure 8 The two periodic PN sequences shown (can also be other pseudo-random sequences, according to system design), they may be adjacent or non-adjacent, and may be separated by other PN sequences or data in the middle, through the received The two periodic PN sequences are time-domain correlated with the local known PN sequence as the pilot signal, and the channel impulse response can be calculated on the two periodic PN sequences; for the convenience of understanding, it needs to be explained that: The channel impulse response here may be a complete channel impulse response, as shown in the figure formed by cascading multiple Figures 9(a) or 9(b);

[0064] Step 702: Accor...

Embodiment 3

[0076] See Figure 11 It is a schematic structural diagram of a frequency discriminator in Embodiment 3 of the present invention, such as Figure 11 As shown, the embodiment of the present invention provides a frequency discriminator, including:

[0077] The calculation module 11A is configured to calculate the partial channel impulse responses on the pseudo-random sequences of the two periods respectively according to the received pseudo-random sequences of the two periods;

[0078] A correlation module 11B, configured to correlate the two partial channel impulse responses, and obtain a related waveform;

[0079] The detection module 11C is configured to perform lead-lag sampling time estimation on the related waveform, and detect the error of the sampling clock frequency according to the output result of the lead-lag sampling time estimation.

[0080]In one implementation, the calculation module 11A is the first calculation module, which is used to correlate the received t...

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Abstract

The embodiment of the invention discloses a method for detecting frequency errors of a sampling clock, a frequency discriminator thereof. The method comprises the following steps: respectively calculating and obtaining partial channel impulse responses on pseudo random sequences of two periods according to the received pseudo random sequences; correlating the two partial channel impulse responsesto acquire related waveforms; and performing lead-lag sampling time estimation on the related waveforms, and detecting errors of frequency of the sampling clock according to output results of the sampling time estimation. The frequency discriminator comprises a calculation module, a relation module and a detection module. Correspondingly, the embodiment of the invention also discloses a method anda system for synchronizing the sampling time; and impacts of small delay multipath can be mutually counteracted by constructing the channel impulse responses symmetric about a main path on the periphery of the main path so as to obtain the sampling clock without frequency errors, and achieve synchronization of the sampling time. The method has moderate complexity.

Description

technical field [0001] The invention relates to the field of signal processing, in particular to a sampling clock frequency error detection method, a frequency discriminator, and a sampling time synchronization method and system. Background technique [0002] In DS-CDMA (Direct Sequence Code Division Multipule Access, Direct Sequence Code Division Multiple Access) or other systems that use PN (Pseudo Noise, pseudo-random) codes for synchronization, such as DTMB (Digital Terrestrial Multimedia Broadcasting, international terrestrial digital television broadcasting) , using the lead-lag sampling time estimation technique for sampling time synchronization is a commonly used method. [0003] The principle of lead-lag sampling time estimation is as follows figure 1 shown. Two PN signals are generated by VCO (Voltage-Controlled Oscillator, Voltage Controlled Oscillator), one is the advance signal Early Code, which is half a chip ahead of the accurate timing (pilot signal, known ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04W24/00H04B17/00H04B17/345
Inventor 胡宇鹏蔡朝辉
Owner HUAWEI TECH CO LTD
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