Cache memory device, arithmetic processing unit, and its control method

A high-speed cache and control method technology, applied in the direction of electrical digital data processing, calculation, static memory, etc., to achieve the effects of reducing power consumption, avoiding performance degradation, and reducing circuit assembly area

Inactive Publication Date: 2010-03-31
FUJITSU LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0058] The present invention solves the problem of existing cache alternate registers

Method used

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  • Cache memory device, arithmetic processing unit, and its control method
  • Cache memory device, arithmetic processing unit, and its control method
  • Cache memory device, arithmetic processing unit, and its control method

Examples

Experimental program
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Embodiment Construction

[0081] An example of an embodiment of the cache line alternation register will be described below with reference to the drawings.

[0082] Figure 8 The overall structure of the CPU of this embodiment is shown.

[0083] Figure 8 The structure of CPU 1 with figure 1 The structure of the CPU 101 shown is substantially the same. CORE2 corresponds to figure 1 CORE 102, SU 3 corresponds to figure 1 SU 103, IU4 corresponds to figure 1 IU 104, EU 5 corresponds to figure 1 EU 105, IF-LBS 6 corresponds to figure 1 IF-LBS 106, OP-LBS 7 correspond to figure 1 The OP-LBS 107, SX 10 corresponds to figure 1 SX 108, SYSTEM BUS 11, Memory 12 respectively correspond to figure 1 SYSTEM BUS 109, Memory 110.

[0084] In this embodiment, IF-CLAR (Cache Line Alternation Register: cache line alternation register) 8 and OP-CLAR 9 are newly added.

[0085] Figure 9 The structure of the cache line alternation register CLAR of this embodiment is shown, and figure 2 A comparison reveals ...

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PUM

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Abstract

The invention provides a cache memory device, an arithmetic processing unit and its control method. The cache memory device is structured to include a data holding part including a plurality of ways having a plurality of cache lines, an alternating data register for holding data for one of the cache lines of the data holding part or for part of the cache lines, an alternating address register forholding index addresses indicating a defective cache line where a failure occurs in the data holding part and a failure occurrence part in the defective cache line, an alternating way register for holding information of a way containing the failure occurrence part, an address matching circuit for comparing an index address to be used for access whenthe data holding part is to be accessed with an index address of the alternating address register, and a way matching circuit for comparing way information to be used for the access when the data holding part is to be accessed with way information held by the alternating way register.

Description

technical field [0001] The present invention relates to a cache device, an arithmetic processing device, and a control method thereof having a cache line alternate register for relieving a defect in a cache line. Background technique [0002] As a conventional remedy for cache stuck-at faults, methods such as block regression and WAY regression are used. In block degradation and WAY degradation, the number of cache failures is observed in WAY units of the cache, and when the number of failures occurring per unit time exceeds a predetermined threshold, block or WAY is cut off. The function of cutting off the faulty cache line and its WAY when the threshold is exceeded for the first time is called block regression. In block degradation, 1 line of data is cut off. When a fault occurs in data other than the cache line where the block degenerates, the object of block degeneration is switched to the cache line and WAY where the fault occurred last. That is, the fault relief bas...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F12/08
CPCG11C29/808G06F11/00G06F12/0895G06F12/08G06F11/07G06F12/14
Inventor 今井裕之清田直宏本车田强
Owner FUJITSU LTD
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