DMA controller on basis of massive data transmitting
A DMA controller and controller technology, applied in the direction of electrical digital data processing, instruments, etc., can solve the problems of large data volume, low DMA transmission efficiency, and low transmission efficiency
Inactive Publication Date: 2011-05-04
BEIJING MXTRONICS CORP +1
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Problems solved by technology
Although this effectively avoids the time spent by the CPU repeatedly fetching and moving data, for mass data transmission, due to the large amount of data, it still takes a long time to transmit byte by byte, so the transmission efficiency is still low
In addition, in the existing DMA transfer, if peripherals such as UART only have a byte-type buffer, the DMA controller only uses the lower 8 bits of the bus for transfer, which reduces the utilization of the bus, and the DMA transfer efficiency is also low. relatively low
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[0083] The technical solution of the present invention will be described in more detail below with reference to the drawings and embodiments.
[0084] Such as figure 2 As shown, the DMA controller of the present invention includes a bus interface, a register bank, a state machine, a memory management unit and a data buffer area, the bus interface is connected with the bus of the controller, and the data buffer area is connected to two external devices; the controller passes through the bus interface Configure and manage the register group, the configuration result of the register group controls the working state of the state machine, and the state machine controls the memory management unit to complete the data exchange between the data buffer area and the external device according to the working state of the state machine;
[0085] The register group includes: a block number counter, a sub-block number counter, a byte counter, and a public register composed of a data source ...
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The invention relates to a DMA controller on basis of massive data transmitting. The configuration of a public register, a byte counter, a block counter and a subblock counter can realize byte data transmission, block data transmission and subblock data transmission; the byte data transmission and the subblock data transmission are suitable for the condition that a data source cache region and a data purpose cache region are different; the block data transmission is suitable for the condition that the data source cache region and the data purpose cache region are the same; and the transmission process is finished by changing the logic address thereof. The technical scheme of the invention can be adopted to ensure that the data of the data source cache region and the data of the data purpose cache region are transmitted at one beat, greatly quickening the data amount of DMA transmission and improving transmission efficiency.
Description
technical field [0001] The invention relates to a DMA structure, in particular to a DMA controller based on mass data transmission. Background technique [0002] In a system containing a central processing unit (CPU), in order to improve CPU utilization efficiency and data transmission rate, during mass data transmission operations, Direct Memory Access Control (DMA) is usually used to operate data. The DMA operation is implemented through a DMA controller (DMA Controller, DMAC). There are two types of DMA controllers: selective type and multi-channel type. The DMA controller involved in the present invention is selective type, that is, multiple hardwares are physically connected, and only one hardware is allowed logically, that is, only one hardware can be used in a certain period of time. A hardware service. [0003] Such as figure 1 As shown, in the existing traditional DMA structure, the DMA transfer initiated by the peripheral is usually to fetch data from the FIFO o...
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IPC IPC(8): G06F13/28
Inventor 宗宇谢俊玲张志永
Owner BEIJING MXTRONICS CORP