Binary floating point translation method aiming at SSE2 instructions

Abstract

The invention discloses a binary floating point translation method aiming at SSE2 instructions in the technical field of dynamic binary translation, which comprises the following steps of: constructing a middle floating point instruction set aiming at the SSE2 instructions; translating front end source machine floating point instructions into middle floating point instructions, and mapping instruction operands positioned in a front end floating point register into a virtual register virtualized by a memory; according to operation codes and operation types of the middle floating point instructions, obtaining the number and the type of the operands of each middle floating point instruction, and mapping the operands in the virtual register into a back end floating point register through a register mapping function; and according to the operation codes and the operands of the middle floating point instructions, translating the middle floating point instructions in the back end floating point register into the SSE2 instructions of an X86 system, and storing the SSE2 instructions in a Tcache. The binary floating point translation method reduces the coupling of a front end floating pointsystem and a back end floating point system, realizes the distributive replacement of a target end register, reduces the accessing and saving expenses, and is suitable for a three-phase dynamic binary translation system of a multi-source single-target platform.

Description

technical field [0001] The invention relates to a method in the technical field of dynamic binary translation, in particular to a binary floating-point translation method for SSE2 instructions. Background technique [0002] Dynamic binary translation technology is an important research direction in the current computer field. It is a technology that can directly translate binary executable files, so as to solve the problem of software transplantation. Generally speaking, different processors support different instruction set architectures (ISAs), such as Intel x86, MIPS, POWERPC and other architectures. Applications developed for one architecture cannot run on another architecture, which limits the application and promotion of software. If hardware technology is used, that is, adding corresponding units on the processor to be compatible with other processors will greatly reduce efficiency while increasing power consumption; and if software translation technology such as bin...

AI Technical Summary

Problems solved by technology

This method has the advantages of rich instructions, but the stack organization form of floating-point registers brings great inconvenience to the operation of registers and brings great challenges to programmers.

[0007] After searching, it is also found that in some three-phase dynamic binary translation systems, a simplified processing method is adopted. Taking the addition instruction as an example, this technology first pushes the two addition source operands into the floating-point register stack, that is, the values ​​of the operands are respectively Load it into ST(0), ST(1), and then perform the addition operation of the values ​​of these two registers (some addition instructions include pop-up operations after operations, while others do not, here we use instructions that include pop-up operations), and get The result is stored in ST(0), ST(1) has been popped up in the operation instruction, and then ST(0) is stored in the corresponding memory, and the stack is popped. At this time, the register stack is cleared, and the next floating-point instruction process Continue this process, but the efficiency of this technique is poor. Each floating-point operation will include three memory access operations, which has a large overhead; in addition, the use efficiency of floating-point registers is also low and has not been fully utilized.