Method for sorting semiconductor element, method for fabricating semiconductor device, and semiconductor device
A manufacturing method and semiconductor technology, which can be used in semiconductor devices, semiconductor/solid-state device testing/measurement, electric solid-state devices, etc., and can solve problems such as rising manufacturing costs
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Method used
Image
Examples
no. 1 example
[0082] A first embodiment of the method for selecting a defect-free semiconductor element according to the present invention will be described with reference to the drawings.
[0083] figure 1 is a flowchart showing the selection process of the semiconductor element in this embodiment.
[0084] In this embodiment, in the wafer processing step 10, a plurality of semiconductor elements are formed on one main surface of a semiconductor substrate (semiconductor wafer).
[0085] Next, protruding electrodes (bumps) are formed on the respective semiconductor elements formed on the semiconductor substrate as terminals for external connection (bump forming step 20 ).
[0086] At this time, an identification bump is provided for at least one semiconductor element formed outside the active area of the semiconductor substrate. The semiconductor element provided with the identification bump was used as a reference semiconductor element.
[0087] Next, each semiconductor element forme...
no. 2 example
[0138] A second embodiment of the method for selecting a non-defective chip according to the present invention will be described with reference to the drawings.
[0139] In this embodiment, a plurality of semiconductor elements are used, and the bumps 261 for identification are arranged for each semiconductor element, wherein a part of the semiconductor element is included in the effective area of the above-mentioned semiconductor substrate (enclosed by the dotted circle ES). region), while the other part is outside the valid region.
[0140] This embodiment is characterized by the arrangement structure of the bumps on the plurality of non-product semiconductor elements (non-product semiconductor chips) and the utilization method of the plurality of non-product semiconductor elements (non-product semiconductor chips).
[0141] That is, if Figure 9A As shown, a plurality of semiconductor elements (non-productized semiconductor chips) are partly included in the effective are...
PUM
Login to View More Abstract
Description
Claims
Application Information
Login to View More 