Time sequence adjusting method for internal IC (integrated circuit) bus, corresponding device and system thereof
An internal integrated circuit, bus timing technology, applied in electrical digital data processing, instruments, etc., can solve the problems of small adjustment range, timing error, small C bus adjustment range, etc., to reduce timing errors and efficient signal transmission. Effect
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Embodiment 1
[0035] The embodiment of the present invention provides a kind of I 2 The C bus timing adjustment method, in order to facilitate the understanding of the method provided by the embodiment of the present invention, firstly, a brief description is given to each device in the system that executes the method, and the system includes at least two through I 2 C bus to communicate with devices due to the I 2 The C bus is a serial bus. Only one device sends data to another device at the same time, that is, the data transmitted on SDA has only one direction at a time. In order to be able to guarantee I 2 The timing on the C bus is correct, in the embodiment of the present invention 2 A programmable logic device is added to the C bus, and the programmable logic device controls the SDA output timing to reduce the I2 purpose of timing errors on the C bus. In order to facilitate the description of the following text, I will be used 2 At least two devices communicating on the C bus are ...
Embodiment 2
[0045] The embodiment of the present invention provides a kind of I 2 C bus timing adjustment method, including:
[0046] Step A1: receiving the signal on the SCL bus and the signal on the SDA bus, and outputting the SCL signal;
[0047] Wherein, it should be noted that the device for performing step A1 may be a programmable logic device, which is equivalent to a transmission line at this time, and does not know the direction of transmission signals on SDA and SCL. The logic device is equivalent to a channel for the signal transmitted on the SCL bus. In addition to detecting the signal on the SCL, the signal on the SCL can be directly output without any processing.
[0048] Step A2: Determine whether I is received 2 C start signal, if yes, go to step A3;
[0049] Among them, one I of the logic device in step A2 2 C bus interface with a device's I 2 C bus interface connected to another I in the logic device 2 C bus interface with another device's I 2 The C bus interface ...
Embodiment 3
[0081] The embodiment of the present invention provides an internal integrated circuit I 2 C-bus timing adjuster, see Figure 6 As shown, the inter-integrated circuit I 2 The C-bus timing adjustment device includes: a receiving unit 11 , a judging unit 21 , a delay unit 31 and a sending unit 41 .
[0082] Among them, the receiving unit 11 is used to receive I 2 The signal on the C bus, that is, receiving the SCL signal and the SDA signal;
[0083] Judging unit 21, for judging I according to the SCL signal and SDA signal received 2 The direction of signal transmission on the C bus;
[0084] The delay unit 31 is used to delay the signal transmitted on the SDA by T according to the determined direction when the SCL signal is at each falling edge;
[0085] The sending unit 41 is configured to output the signal on the SCL without processing, and output the signal on the SDA bus after a delay time T.
[0086] An internal integrated circuit I provided by the above embodiments o...
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