Shallow groove, manufacturing method thereof and shallow groove isolation structure

Abstract

The invention relates to a shallow groove, a manufacturing method thereof and a shallow groove isolation structure, wherein the manufacturing method of the shallow groove comprises the following steps of: providing a semiconductor substrate provided with a mask layer; etching the mask layer to ensure that the cross section of the mask layer in the direction parallel to the width of the shallow groove is rectangular or square; and taking the mask layer as a mask to form the shallow groove on the semiconductor substrate by using halogen-containing plasma, wherein the cross section of side wall of the shallow groove in the width direction is concave. Compared with the prior art, the shallow groove structure with the concave side wall is more convenient for filling the shallow groove. Besides, because the mask layer of which the cross section is rectangular or square is used as the mask for etching the shallow groove, the deviation between the original design size and the actual manufacturing size of the shallow groove is uniform.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a shallow trench, a manufacturing method thereof and a shallow trench isolation structure. Background technique [0002] The development direction of semiconductor integrated circuits is to increase density and shrink components. In the manufacture of integrated circuits, the isolation structure is an important technology, and the components formed on the silicon substrate must be isolated from other components. With the advancement of semiconductor manufacturing technology, shallow trench isolation (Shallow Trench Isolation, STI) technology has gradually replaced other isolation methods such as local oxidation of silicon (LOCOS) used in traditional semiconductor device manufacturing. [0003] The manufacturing method of the existing shallow trench isolation structure generally includes: oxidizing the silicon wafer in a high-temperature oxidation furnace tube, forming ...

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Problems solved by technology

It can be seen from the above description that in order to better fill the oxide layer in the shallow trench, it is necessary to use a more complicated process.

[0005] Moreover, the deviation between the size of the shallow trench manufactured by the prior art and the original design size is not uniform, for example, when the design size is 70nm, the size of the manufactured shallow trench is 56nm, and its size deviation is 14nm , and when the design size is 60nm, the size of the manufactured shallow trench is still 56nm, and its size deviation is 4nm, which causes the size of the manufactured semiconductor device to deviate from the expected size, which will further affect the performance of the semiconductor device

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