Multiple time programmable (mtp) pmos floating gate-based non-volatile memory device for general-purpose cmos technology with thick gate oxide

Abstract

A multiple time programmable (MTP) memory cell, in accordance with an embodiment, includes a floating gate PMOS transistor, a high voltage NMOS transistor, and an n-well capacitor. The floating gate PMOS transistor includes a source that forms a first terminal of the memory cell, a drain and a gate. The high voltage NMOS transistor includes a source connected to ground, an extended drain connected to the drain of the PMOS transistor, and a gate forming a second terminal of the memory cell. The n-well capacitor includes a first terminal connected to the gate of the PMOS transistor, and a second terminal forming a third terminal of the memory cell. The floating gate PMOS transistor can store a logic state. Combinations of voltages can be applied to the first, second and third terminals of the memory cell to program, inhibit program, read and erase the logic state.

Description

Multiple-Time Programmable Nonvolatile Memory Devices with Thick Gate Oxide This application has a priority date of April 21, 2006, a priority number of US60 / 793,770, US11 / 498,672, US11 / 508,771, and a Chinese national application number of 200710101379.5. A divisional application of the application for programming non-volatile memory devices". priority claim This application claims U.S. Patent Application No. 11 / 508,771, filed August 23, 2006, U.S. Patent Application No. 11 / 498,672, filed August 2, 2006, and U.S. Provisional Priority of Patent Application No. 60 / 793,770. Each of these applications is incorporated herein by reference. technical field Embodiments of the present invention relate to multiple times programmable (MTP) memory devices. Background technique US Patent No. 6,271,560, which is hereby incorporated by reference, teaches the use of a CMOS-compatible voltage-programmable floating-gate avalanche-type PMOS (FAMOS) device structure as a non-volatile m...

AI Technical Summary

Problems solved by technology

This limits the application of existing cells for MTP to relatively thin (less than 10nm, 3.3V I / O devices) gate oxides requiring erase voltages below ~12V

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