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Static random access memory capable of increasing write surplus capacity

A technology of static random access and writing margin, which is applied in the direction of static memory, digital memory information, information storage, etc., and can solve the problems of increasing the writing margin of the static random access storage unit and unable to guarantee the writing margin , to achieve the effect of increasing the write margin

Active Publication Date: 2015-02-11
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0012] In order to overcome the disadvantages of the SRAM unit in the prior art that cannot guarantee the writing margin, the main purpose of the present invention is to provide a SRAM, which provides a controllable power supply voltage or The negative terminal voltage of the power supply can achieve the purpose of increasing the writing margin of the static random access memory unit

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  • Static random access memory capable of increasing write surplus capacity
  • Static random access memory capable of increasing write surplus capacity
  • Static random access memory capable of increasing write surplus capacity

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Embodiment Construction

[0031]The implementation of the present invention is described below through specific examples and in conjunction with the accompanying drawings, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific examples, and various modifications and changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.

[0032] Please also refer to image 3 and Figure 4 , image 3 It is a structural schematic diagram of a first preferred embodiment of a static random access memory that includes a static random access memory cell array and can increase a write margin in the present invention, Figure 4 for image 3 The circuit structure diagram of the static random access memory cell A. As shown in the f...

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Abstract

The invention provides a static random access memory capable of increasing write surplus capacity, at least comprising a static random access memory cell array which includes a plurality of static random access memory cells arranged in array form as well as a controllable power supply circuit which is connected with the static random access memory cell array and is used for providing controllable voltage for each static random access memory cell. Under the reading and hold-on mode, power supply voltage and power supply negative terminal voltage of each line of the static random access memory cell array are constant, when executing write operation, the power supply voltage of the line in which the operated static random access memory cell is located is reduced or the power supply negative terminal voltage of the line in which the operated static random access memory cell is located is improved, voltages in other lines are not changed, thus the acceptable low lever range of the static random access memory cell of the invention is widened and the write capacity of the static random access memory of the invention is increased.

Description

technical field [0001] The present invention relates to a semiconductor memory device, in particular to a static random access memory capable of increasing write margin. Background technique [0002] The threshold voltage Vt is an important electrical parameter of the MOS transistor, and is also an important control parameter in the manufacturing process. The size and consistency of Vt have a decisive impact on the performance of circuits and even integrated systems. The mathematical expression for the threshold voltage is: [0003] Vt=Ψms-Qox / Cox+Qb / Cox+2Ψb [0004] In the formula, Qox is the fixed positive charge density in the gate oxide layer; Cox is the gate oxide layer capacitance per unit area, which is inversely proportional to the gate oxide layer thickness tox; Qb is the substrate doping impurity concentration (charge in the depletion layer), and the NMOS tube adopts P-type silicon is used as the substrate, and this value is negative. PMOS transistors use N-type...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C11/412
Inventor 胡剑
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP