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Semiconductor memory device

A storage device, semiconductor technology, applied to SRAM. field, can solve the problem of SRAM writing margin reduction, achieve the effect of increasing writing margin and suppressing the increase of chip area

Active Publication Date: 2020-09-01
RENESAS ELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

For this reason, there is a problem that the write margin of the SRAM is reduced.

Method used

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  • Semiconductor memory device
  • Semiconductor memory device
  • Semiconductor memory device

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0036]

[0037] figure 1 is an explanatory diagram of the outline of the overall configuration of the semiconductor memory device according to Embodiment 1.

[0038] Such as figure 1 As shown, the semiconductor memory device is composed of a memory cell array 1 having a plurality of memory cells MC arranged in a matrix. The memory cell array 1 is composed of: a plurality of word lines provided corresponding to each row of memory cells; and a plurality of bit line pairs provided corresponding to each column of memory cells. Here, the memory cell MC is a so-called dual-port cell consisting of a first word line WLA and a corresponding first pair of bit lines BLA and / BLA, and a second word line WLB and a corresponding The second bit line pair BLB and / BLB.

[0039] The semiconductor memory device is composed of: a first row selection driver circuit 2A that selects a first word line WLA; and a first column selection circuit 3A that generates a column selection signal for se...

Embodiment 2

[0141] Figure 11 is an explanatory diagram of the configuration of the first write assist circuit 5A according to Embodiment 2.

[0142] Such as Figure 11 As shown, a plurality of circuits of the first write driver circuit 6A and a plurality of circuits of the first write assist circuit 5A are respectively provided corresponding to a plurality of columns of memory cells. A plurality of circuits of the first write assist circuit 5A share the source node WBSA. Figure 11 A case is illustrated in which adjacent circuits of the first writing circuit 5A share a common source node WBSA. This also applies to other write assist circuits. The second write assist circuit 5B is also provided in the same manner as in the first write assist circuit 5A.

[0143] In the disturbance writing described above, when the threshold voltage of the access MOS transistor NQ5 on the disturbance side becomes lower, the potential rise of the bit line on the writing side becomes conspicuous. Howeve...

Embodiment 3

[0146] Example 3 illustrates a method for further improving the pressurization capability.

[0147] Figure 12 is an explanatory diagram of the configuration of the first write assist circuit 5AP and the second write assist circuit 5BP according to Embodiment 3.

[0148] Such as Figure 12 As shown, the first write assist circuit 5AP differs from the first write assist circuit 5A in that a buffer BF2A and a third signal wiring ML13A are added.

[0149] The buffer BF2A is coupled to the first signal wiring ML11A, and drives the third signal wiring ML13A according to the signal level transmitted to the first signal wiring ML11A.

[0150] This also applies to the second write assist circuit 5BP; therefore, its detailed explanation is not repeated. The output node NBSTA is coupled to the signal wiring ML11A, and the node WBSA is coupled to the signal wiring ML12A. Two signal wirings ML11A and ML12A are arranged in parallel with the bit lines, and are arranged over the memory c...

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Abstract

A semiconductor storage device provided can increase a write margin and suppress increase of a chip area. The semiconductor storage device includes plural memory cells arranged in a matrix; plural bit-line pairs arranged corresponding to each column of the memory cells; a write driver circuit which transmits data to a bit-line pair of a selected column according to write data; and a write assist circuit which drives a bit line on a low potential side of the bit-line pair of a selected column to a negative voltage level. The write assist circuit includes first signal wiring; a first driver circuit which drives the first signal wiring according to a control signal; and second signal wiring which is coupled to the bit line on the low-potential side and generates a negative voltage by the driving of the first driver circuit, based on inter-wire coupling capacitance with the first signal wiring.

Description

[0001] Cross References to Related Applications [0002] The disclosure of Japanese Patent Application No. 2014-061812 filed on Mar. 25, 2014 including specification, drawings and abstract is incorporated herein by reference in its entirety. technical field [0003] The present invention relates to a semiconductor storage device, in particular to a SRAM (Static Random Access Memory). Background technique [0004] The purpose of advancing miniaturization of transistor elements is to achieve high integration. Along with miniaturization, manufacturing variation becomes large, resulting in significant differences in the properties of transistor elements. Along with miniaturization, there has been progress in ensuring reliability and lowering voltage to reduce power consumption. For this reason, there arises a problem that the write margin of the SRAM decreases. [0005] In response to this problem, a method of preventing failure of the write operation by setting the bit line...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C11/413
CPCG11C7/12G11C8/16G11C11/412G11C11/418G11C11/419G11C7/1096
Inventor 佐野聪明柴田健田中信二薮内诚前田德章
Owner RENESAS ELECTRONICS CORP
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