Malfunction detection method of incremental encoder
An incremental encoder and fault detection technology, which is applied in the direction of instruments, can solve the problems of non-broken fault detection of incremental encoders, achieve accurate detection, and realize the effect of simple circuit
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Method used
Image
Examples
specific Embodiment approach 1
[0022] Specific implementation mode one: the following combination image 3 Describe this embodiment, this embodiment is the detection of the electrical pulse signals A and B of the incremental encoder: the electrical pulse signal A with a phase difference of 90° output by the two code channels of the incremental encoder under normal working conditions XOR with B to obtain the synchronous clock signal Clock, at the rising edge moment of every adjacent cycle of the synchronous clock signal Clock, the states of the electrical pulse signals A and B are at A=1, B=0 and A=0, B = Cycle between 1;
[0023] Define the circuit output state Q2Q1 of two JK flip-flops FF2 and FF1 triggered by rising edges as:
[0024] S 0 =00, normal state sequence;
[0025] S 1 =01, normal state sequence;
[0026] S 2 =10, fault state sequence;
[0027] S 3 = 11, regardless of state sequence;
[0028] In every two adjacent cycles of the synchronous clock signal Clock, at the rising edge of the p...
specific Embodiment approach 2
[0032] Specific implementation mode two: the following combination image 3 , Figure 4 and Figure 5 Describe this embodiment. The difference between this embodiment and Embodiment 1 is that the electric pulse signal A is 90° ahead of the phase of B, and the S of Q2Q1 0 The circuit output state of =00 corresponds to the state of electric pulse signal A=0, B=1, the S of Q2Q1 1 The circuit output state of =01 corresponds to the state of electric pulse signal A=1, B=0.
[0033] The design process of the fault detection circuit to realize the detection method of the present invention is as follows,
[0034] First, two rising-edge triggered JK flip-flops FF2 and FF1 are used, and the circuit output state Q2Q1 has four states 00, 01, 10 and 11.
[0035] Define the circuit state:
[0036] S0=00 is the normal state sequence;
[0037] S1=01, it is normal state sequence;
[0038] S2=10, it is the fault state sequence;
[0039] S3=11, it is irrelevant state sequence, the circuit w...
specific Embodiment approach 3
[0045] Specific implementation mode three: the following combination Image 6 Figure 10 Describe this embodiment. The difference between this embodiment and Embodiment 1 is that the electric pulse signal A lags behind the phase of B by 90°, and the S of Q2Q1 0 The circuit output state of =00 corresponds to the state of electric pulse signal A=1, B=0, the S of Q2Q1 1 The circuit output state of =01 corresponds to the state of electric pulse signal A=0, B=1.
[0046] The implementation circuit of this embodiment can be obtained by repeating the design process of the second embodiment in terms of design principles, and the entire fault detection circuit diagram that realizes the detection methods of the second and third embodiments simultaneously Image 6 shown. Through the XOR of the electric pulse signals A and B generated by the encoder, the pulse output diagram of the clock signal Clock required by the fault detection circuit is obtained, and the state machine circuit is ...
PUM
Login to View More Abstract
Description
Claims
Application Information
Login to View More 