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Packaging substrate and chip packaging construct

A packaging substrate and chip packaging technology, applied in the direction of electrical components, electrical solid devices, circuits, etc., can solve the problems of easy fracture or deformation, easy damage, uneven stress distribution of flexible packaging substrates, etc., to reduce excessive Etching, reducing fracture phenomenon, increasing the number of times and the effect of life

Inactive Publication Date: 2011-09-21
CHIPMOS TECH INC
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  • Summary
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  • Description
  • Claims
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Problems solved by technology

[0005] However, since the width of the planar region 1220 is larger than the line segments of the first leads 120 and the second leads 122, when the flexible packaging substrate 1 is repeatedly bent and flexed, the stress distribution will be uneven, resulting in variations in the width of adjacent leads. The junction of the plane region 1220 and the line segment of the second lead 122 and the position close to the junction on the first lead 120 are relatively prone to breakage or deformation
In other words, the existing flexible packaging substrate 1 is still prone to damage even under normal use conditions, thereby making the electronic device unable to operate normally.

Method used

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  • Packaging substrate and chip packaging construct
  • Packaging substrate and chip packaging construct
  • Packaging substrate and chip packaging construct

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Embodiment Construction

[0016] See figure 2 , figure 2 is a schematic diagram of a chip package structure 7 according to a specific embodiment of the present invention. As shown in the figure, the chip packaging structure 7 of the present invention includes a packaging substrate 3 and a chip 4 , wherein the packaging substrate 3 is used to carry the chip 4 . In practical applications, the packaging substrate 3 can be provided with multiple chips 4 according to actual needs. In addition, in practice, the position of the chip 4 is determined according to the needs of users or designers, and is not limited to the specific embodiments listed in this specification.

[0017] The package substrate 3 includes a flexible dielectric layer 30 and a conductive layer 32 . The conductive layer 32 is disposed on the flexible dielectric layer 30 and used for electrically connecting to the chip 4 . caution, figure 2 It is a partial schematic diagram of the flexible dielectric layer 30 and the conductive layer...

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Abstract

The invention provides a packaging substrate for carrying a chip. The packaging substrate comprises a flexible dielectric layer and a conductive layer, wherein the conductive layer is arranged on the flexible dielectric layer and electrically connected with the chip and comprises a first lead wire and a second lead wire; the second lead wire is adjacent to the first lead wire and has a plane region; and the plane region comprises an adjacent region adjacent to the first lead wire, and the adjacent region is provided with at least one groove so that the adjacent region forms at least one sub-lead wire.

Description

technical field [0001] The present invention relates to a packaging substrate and a chip packaging structure, and in particular, the present invention relates to a packaging substrate and a chip that can reduce the breakage of the leads when the packaging substrate is bent and flexed by means of the arrangement of grooves on the leads. Package construction. Background technique [0002] With the development of information electronic products and the needs of consumers, electronic products are gradually developing in the direction of thinner, smaller and more flexible than the previous designs. Compared with rigid substrates, flexible packaging substrates have better flexural properties, and can meet the needs of higher pin count bonding and provide more flexible circuit configuration designs. Therefore, flexible packaging substrates are widely used, and its application range includes mobile phones, notebook computers, digital cameras, e-books, and liquid crystal displays. ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/498
Inventor 李明勋陈必昌
Owner CHIPMOS TECH INC
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