Programmable signal routing systems having low static leakage

Abstract

Parasitic static leakage current through input terminals of bus-accessing multiplexers is minimized by automatically forcing as many as practical of the bus lines into a high impedance state where all drivers of the lines are in a high impedance output state. Thus parasitic current sinking or current sourcing leakage paths through the bus-accessing multiplexers are cut off. The method is of particular utility in a low power FPGA that desirable has low static current leakage when in a static state.

Description

technical field [0001] The present disclosure generally relates to programmable signal routing systems such as found in field programmable gate arrays (FPGAs) or other programmable logic devices (PLDs). The present disclosure relates more particularly to structures and methods for reducing quiescent current leakage associated with such programmable signal routing systems. Background technique [0002] A Field Programmable Gate Array (FPGA) device can be characterized as consisting of a monolithic, integrated circuit (IC) that typically has four main features, namely: Configurable Logic Blocks (CLBs), Configurable Signal routing interconnects, configurable input / output blocks (CIOBs) and configuration components for programmably configuring CLBs, interconnects and CIOBs. [0003] FPGAs can be designed to be used in a variety of environments. One such environment requires minimized power consumption at least when the FPGA is in standby mode. To date, no close attention has ...

AI Technical Summary

Problems solved by technology

To date, no close attention has been paid to DC power leakage (static leakage) due to configurable signal routing interconnects of FPGAs and similar reconfigurable logic devices

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