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Method for manufacturing p-n junction of Ge/Si solar battery by dipping method

A solar cell, n-type technology, applied in the direction of sustainable manufacturing/processing, circuits, electrical components, etc., can solve the problems of high risk of silane gas, difficulty in industrialization, high consumption of waste gas treatment, etc., to save silicon germanium raw materials, Effect of improving photoelectric conversion efficiency and improving productivity

Inactive Publication Date: 2012-10-10
高文秀
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] The main methods of growing SiGe heterojunction materials are molecular beam epitaxy (MBE), selective epitaxial growth (SEC), ultra-vacuum chemical vapor phase epitaxy (UHV / CVD) and reduced pressure chemical vapor deposition (RPCVD), etc., MBE High precision, capable of real-time control, but expensive equipment, high cost, difficult to achieve industrialization
The CVD method is a technology in which gaseous substances are deposited on the surface of the substrate by chemical reaction to form the required epitaxial layer. It can effectively reduce the contamination of the substrate and the epitaxial layer, thereby obtaining high-quality SiGe materials, but the silane gas it uses It is very dangerous, and the remaining silane waste gas is easy to be natural and explosive, which makes the consumption of waste gas treatment high

Method used

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  • Method for manufacturing p-n junction of Ge/Si solar battery by dipping method
  • Method for manufacturing p-n junction of Ge/Si solar battery by dipping method

Examples

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example 1

[0026] Example 1: Add n-type polysilicon and a certain proportion of Ge in the temperature control pot 6, so that the atomic percentage of Ge content in its Si-Ge alloy solution 5 is 20%, and then close the whole system, and the whole system is kept under high-purity argon gas Environment. Heat the temperature control pot, fully dissolve the n-type polysilicon and an appropriate amount of Ge, and keep the temperature of the Si-Ge alloy solution at 1450°C. The holder clamps the p-type polysilicon, and preheats the free end surface of the p-type polysilicon substrate. The preheating temperature is 1200°C, the depth of its entry into the liquid Si-Ge surface is controlled at 0.2 mm, and the dipping time is 0.3 seconds. In order to ensure that the thin layer of Si-Ge alloy solution dipped on the p-type polysilicon substrate is not rapidly solidified, the p-type polysilicon substrate dipped in the n-type Si-Ge alloy solution is quickly moved to the cooling system and slowly cooled ...

Embodiment 2

[0027]Embodiment 2: other conditions are the same as embodiment 1, make the atomic percent of Ge content in its Si-Ge alloy solution be 40%, n-type Si-Ge alloy solution temperature is controlled at 1475 ℃, p-type polysilicon substrate preheating temperature reaches 1100°C, the p-type polysilicon substrate is quickly dipped into the n-type Si-Ge alloy solution, the depth of entering the liquid surface is controlled at 0.4mm, the dipping time is 0.4 seconds, and then quickly put into the cooling system for directional solidification, so that the temperature drops to At 1100°C, there will be a Ge-enriched layer on the surface with a thickness of 145 μm, and the buffer layer Si 1-x Ge x (0

Embodiment 3

[0028] Embodiment 3: other conditions are the same as embodiment 1, make the atomic percent of Ge content in its Si-Ge alloy solution be 60%, n-type Si-Ge alloy solution temperature is controlled at 1480 ℃, p-type polysilicon substrate preheating temperature reaches 1000°C, the p-type polysilicon substrate is quickly dipped into the n-type Si-Ge alloy solution, the depth of entering the liquid surface is controlled at 0.6mm, the dipping time is 0.7 seconds, and then quickly put into the cooling system for directional solidification, so that the temperature drops to At 1000°C, a Ge-rich layer will be enriched on its surface, with a thickness of 196 μm, and the buffer layer Si 1-x Ge x (0

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Abstract

The invention relates to a method for manufacturing a p-n junction of a Ge / Si solar battery by a dipping method, which comprises the following steps of: adding highly-pure Ge in a certain proportion into n-type Si in a heat-resisting crucible in a sealed and highly-pure argon shielding atmosphere, and heating and melting the mixture to form Si-Ge alloy solution; clamping p-type polysilicon with aholder, preheating the free end face of a substrate of the p-type polysilicon to a certain temperature and fast dipping the p-type polysilicon in the n-type Si-Ge alloy solution; and then slowly cooling the p-type polysilicon dipped in the n-type Si-Ge alloy solution for directional solidification and annealing treatment to form the p-n junction of the solar battery on an interface of the p-type polysilicon and the n-type Ge-rich layer. Through the method, the release of hazardous substances is controlled by argon shielding, so pollution to the environment is reduced; and the Ge-rich layer isobtained by dipping the substrate of the p-type polysilicon in the n-type Si-Ge alloy solution and then slowly performing directional solidification to enrich the Ge on the surface of the substrate of the polysilicon, and greatly improves p-n carrier mobility, thereby greatly improving the conversion efficiency of the solar battery. The method has the advantages of simple manufacturing process, no material waste and great significance to large-scale production.

Description

Technical field: [0001] The invention relates to a semiconductor device and solid-state devices not included in other categories, and more specifically relates to a method for making p-n junctions of Ge / Si solar cells by dipping method. Background technique: [0002] The p-n junction is the core of a polysilicon solar cell, and the material and manufacturing quality it uses will directly affect the conversion efficiency of the solar cell. Silicon is the most widely used semiconductor, but silicon is an indirect bandgap semiconductor with a fixed bandgap width, which limits the further expansion of its application. With the in-depth research of "energy band engineering" and "material engineering", silicon-based heterostructures have emerged as the times require, providing a strong guarantee for tailoring energy bands, designing heterostructures, adjusting electrical and optical properties, and manufacturing new functional devices . Polycrystalline SiGe is expected to become...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L31/18
CPCY02P70/50
Inventor 高文秀赵百通
Owner 高文秀