Method and equipment for adjusting reference unit threshold parameter and testing system

A reference unit and threshold technology, applied in static memory, instruments, etc., can solve the problems of soaring test costs, prolonging test time, and prolonging test time, so as to achieve the effect of shortening test time, reducing test cost and increasing test time.

Active Publication Date: 2010-10-13
GIGADEVICE SEMICON SHANGHAI INC +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] Although such a solution can solve the individual differences in the electrical performance of each memory chip, it leads to the extension of the test time.
For example, if it takes 2 seconds to adjust the

Method used

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  • Method and equipment for adjusting reference unit threshold parameter and testing system
  • Method and equipment for adjusting reference unit threshold parameter and testing system
  • Method and equipment for adjusting reference unit threshold parameter and testing system

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Embodiment Construction

[0057] In order to make the above objects, features and advantages of the present invention more comprehensible, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0058] refer to figure 2 , shows Embodiment 1 of a method for adjusting reference cell threshold parameters of the present invention, which is used in the parallel testing process of multiple memory chips, and may specifically include the following steps:

[0059] Step 201, performing an erasing operation on the reference units of all the chips to be tested on the testing machine;

[0060] Step 202, measure the current of the reference unit of each chip to be tested, if it meets the first preset condition, enter the next step, otherwise, perform the erasing operation again;

[0061] Step 203, programming the reference units of each chip to be tested;

[0062] Step 204, measure the current of the programmed reference unit, if it...

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PUM

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Abstract

The invention provides a method for adjusting reference unit threshold parameters, which is used in the parallel testing process of a plurality of memory chips and comprises the following steps that: erasing operation is conducted to reference units of all chips to be tested on a testing machine; the current of the reference unit of each chip to be tested is measured, if the current is compliant with a first preset condition, a next step is conducted, and if not, re-erasing operation is conducted to the reference unit; programming operation is conducted to the reference unit of each chip to be tested; if the current of certain programmed reference unit is compliant with a second preset condition, the adjustment of the reference unit is completed and the chip is disconnected with the testing machine; and programming operation is continuously conducted to the chips to be test which are not disconnected with the testing machine until all chips to be tested are disconnected with the testing machine. Since the invention can really realize the parallel testing, the invention has the advantages that the overall testing time of the testing machine is greatly shortened and the testing costis greatly reduced.

Description

technical field [0001] The invention relates to the technical field of semiconductor chip testing, in particular to a method for adjusting reference cell threshold parameters during memory chip testing, a device for adjusting reference cell threshold parameters, and a testing system. Background technique [0002] In order to verify the correctness of memory products, a series of testing procedures will be carried out before the products leave the factory. These memory products may include non-volatile memory products (for example, flash memory Flash, or electrically erasable programmable read-only memory EEPROM, etc.), and may also include one-time programmable OTP memory. [0003] The general test process can include open circuit / short circuit test of product pin (pin), logic function test, electric erasing characteristic test (to judge whether the data in the non-volatile memory can be electrically erased and write new data ), program code test (reading the program code w...

Claims

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Application Information

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IPC IPC(8): G11C29/56
Inventor 胡洪韩飞
Owner GIGADEVICE SEMICON SHANGHAI INC
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