Delay-locked loop

Abstract

The invention discloses a delay-locked loop. The delay-locked loop comprises a voltage-controlled delay line and a plurality of multi-route selectors, wherein the voltage-controlled delay line comprises a plurality of cascaded delay units; each multi-route selector comprises a plurality of differential pair tubes; the grid of each differential pair tube is connected with the output node of a delay unit respectively; one end of the differential pair tube is connected with grounding voltage through a shared current source, while the other end is connected with power voltage through a load device; each multi-route selector also comprises a switch connected between the differential pair tube and the shared current source; and when the output node of one delay unit is switched on, the switch of the differential pair tube connected with the output node is switched on and the last output node of a multi-route selector in front of the multi-route selector connected with the output node is also switched on.

Description

【Technical field】 [0001] The invention relates to the field of delay circuit design, in particular to a delay phase-locked loop. 【Background technique】 [0002] A delay locked loop (DLL) circuit is a circuit that can output a periodic signal that has the same period as an input clock signal and has a certain time delay. [0003] The core component of the delay-locked loop (DLL) is the voltage-controlled delay line (VCDL). The voltage-controlled delay line usually includes several delay units. Its main function is to generate multiple (such as 1 to i) delays with the input signal time (such as t 1 to t i ) of the new output signal. Usually the delay time of each delay unit is designed to be the same, that is, t i -t i-1 Yes, the output signal can be derived by gating the output node between two adjacent delay units. However, it is known from analysis and simulation that when a multiplexer (mux) for gating the output node is added to the output node, since the multiplexe...

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Problems solved by technology

However, it is known from analysis and simulation that when a multiplexer (mux) for gating the output node is added to the output node, since the multiplexer is also a load, it will affect the delay time of each delay unit , the specific performance is that the corresponding delay time is different with the position of the output node

Take the case when the gated output node needs to be switched, when the two gated output nodes are connected to the same multiplexer, the load changes caused by the multiplexer during switching can offset part of each other, which is not particularly obvious ; However, when the two selected output nodes are connected to two different multiplexers, the load change caused by the multiplexer will produce a sudden change, which appears in the simulation as a delay step in the switching process a clear jump of

This situation will limit the accuracy of the delay control and affect the consistency of the delay at all levels of the voltage-controlled delay line

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