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Method of simulating real-time calibration of large time-delay analog source with high precision

An analog source, high-precision technology, used in radio wave measurement systems, instruments, etc., can solve the problem of difficulty in improving the accuracy of digital storage hardware characteristics, and achieve high-precision ranging and positioning requirements, small resource overhead, and low economic costs. Effect

Active Publication Date: 2015-07-01
10TH RES INST OF CETC
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Problems solved by technology

[0003] The purpose of the present invention is to provide a low-consumption, low-cost analog source that does not affect the normal operation of the long-delay analog source for the above-mentioned prior art that is based on asynchronous dual storage technology. work, aiming at improving the delay accuracy

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  • Method of simulating real-time calibration of large time-delay analog source with high precision
  • Method of simulating real-time calibration of large time-delay analog source with high precision
  • Method of simulating real-time calibration of large time-delay analog source with high precision

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Embodiment Construction

[0015] refer to figure 1 . exist figure 1 In the process of high-precision real-time calibration of the long-delay analog source described, the long-delay analog source based on asynchronous dual storage delay starts from the update of the delay setting and is completed in three steps: online delay measurement, error calculation and error correction. Delay self-calibration, in which online delay measurement includes two sub-steps of data marking and tracking and counting. The first two steps of the above three steps are completed in the fine delay stage, and the last step is completed in the coarse delay stage. The specific steps include: in the fine delay stage of the simulated source delay simulation, adding a data mark to the idle bits in the header or tail of a data packet, and setting a special mark register to store the packet head mark. Mark the delayed data, and set a counter with the same frequency as the storage write clock at this stage; the counter tracks the ac...

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Abstract

The invention provides a method of simulating the real-time calibration of a large time-delay analog source with high precision which is low in consumption and low in cost, and is incapable of influencing the normal operation of the large time-delay analogue source, so as to improve a method of improving the time delay precision as an objective. The method comprises the steps of adding data marks to idle bits in several bytes at the head part or the tail part of a database, and installing a special mark register to memorize a packet header mark, and marking delayed data; meanwhile, installing a counter which is synchronous with the frequency of a write block stored at the state; generating a reset pulse to the counter when the time delay set is updated, updating and marking a value of a shifting register and judging whether the value is equal to a value of a mark register, adding 1 to the value of the counter if the value of the shifting register is not equal to the mark register, and completing the time delay online measurement if the value of the counter is equal to the mark register; compensating a time delay error generated by fine time delay by virtue of changing a thick time delay memory terminating address at the coarse time delay state, and completing the real-time delay verification by changing the termination memory address.

Description

technical field [0001] The invention relates to a high-precision realization method of a large time-delay analog source based on asynchronous double-storage delay for ranging or positioning in the field of aerospace deep space measurement and control and radar system measurement. Background technique [0002] In aerospace deep space measurement and control systems and radar systems, long-delay analog sources are widely used for calibration or correction of ranging and positioning. The existing large-delay analog sources are realized through two types of technologies: digital chip delay technology and asynchronous dual-storage technology. The former has high requirements on the quality of the system clock, and it is not easy to make the resolution very small under the condition of large delay, so the application area is not large. The latter uses one slow and one fast asynchronous read and write clock to divide the storage delay into thick and thin, which solves the contradi...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G01S7/40
CPCG01S7/40
Inventor 胡勇沈世科张靖悉李玥黄凯冬
Owner 10TH RES INST OF CETC
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