VLSI (Very Large Scale Integration) structural design method of parallel pipeline deblocking filter

A technology of deblocking and structural design, applied in the field of video encoding and decoding, can solve the problems of consuming computing resources, video quality and bit rate increase computing complexity, etc., to achieve high video quality and eliminate blocking effects

Inactive Publication Date: 2010-11-10
XI AN JIAOTONG UNIV
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Problems solved by technology

However, this improvement in video quality and reduction in bit rate is at the cost of increased computational complexity
In hardware implementation, even aft...

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  • VLSI (Very Large Scale Integration) structural design method of parallel pipeline deblocking filter
  • VLSI (Very Large Scale Integration) structural design method of parallel pipeline deblocking filter
  • VLSI (Very Large Scale Integration) structural design method of parallel pipeline deblocking filter

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Embodiment Construction

[0058] figure 1 In the first embodiment shown, a highly efficient parallel deblocking filter VLSI structure is given. The source video sequence is buffered to two FIFOs through the external bus in units of macroblocks. The data in the FIFOs are organized as four pixels per row / column The form enters the boundary filter, is updated according to the filtering algorithm defined by the H.264 standard, and then passes through the on-chip loop, or temporarily stores on-chip storage, or completes the filtering and outputs the external bus.

[0059] figure 2 The second embodiment shown shows that the filtering algorithm is divided into a five-stage pipeline: reading data, threshold calculation, pre-filtering, filtering, and writing data. Pipeline technology truncates complex combinational logic to obtain a better maximum operating frequency to improve system throughput.

[0060] image 3The optimized storage strategy is given in the third embodiment shown, including storage of the...

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Abstract

The invention discloses a VLSI (Very Large Scale Integration) structural design method oriented to an ultrahigh-definition real-time deblocking filter by adopting a boundary filter based on a five-level pipeline. The method optimizes a mixed filtration order and data output to avoid the stalled waiting of the pipeline, improves the performance of the pipeline, increases the throughput by approximate double in comparison with a single filter design by adopting the parallel double-boundary filter structure, optimizes a storage strategy, a buffer mechanism and the filtration order, develops the on-chip temporary storage of filtration intermediate results for complexing, and lowers the bandwidth requirement for external storage and the requirement for intermediate storage.

Description

technical field [0001] The invention belongs to the field of video encoding and decoding, and in particular relates to a method for designing a VLSI structure of an H.264-based deblocking filter. Background technique [0002] With the rapid development of Internet applications, multimedia technology has been widely used in many fields such as communication, entertainment, medical treatment and military affairs. In multimedia information, video information is the most effective and important form of information transmission for human beings. Due to the large amount of video information data, it takes up a lot of bandwidth in communication and a lot of storage resources in storage. The contradiction between it and the existing limited resources gave birth to video compression technology. Currently the most efficient compression standard is H.264 / AVC. H.264 adopts many new technologies, including loop deblocking filter, to solve the block effect in video under high compressio...

Claims

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Application Information

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IPC IPC(8): H04N7/26H04N19/117H04N19/154H04N19/176H04N19/42H04N19/44
Inventor 兰旭光付强李兴玉贾淑妍郑南宁
Owner XI AN JIAOTONG UNIV
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